Abstract
In this paper, we propose a gate-level NBTI delay degradation model, where the stress voltage variability due to PMOS transistors’ stacking effect is considered for the first time. Experimental results show that our gate-level NBTI delay degradation model results in a tighten upper bound for circuit performance analysis. The traditional circuit degradation analysis leads to on average 59.3% overestimation. The pin reordering technique can mitigate on average 6.4% performance degradation in our benchmark circuits.
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Luo, H., Wang, Y., He, K., Luo, R., Yang, H., Xie, Y. (2007). A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect. In: Azémard, N., Svensson, L. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2007. Lecture Notes in Computer Science, vol 4644. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74442-9_16
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DOI: https://doi.org/10.1007/978-3-540-74442-9_16
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-74441-2
Online ISBN: 978-3-540-74442-9
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