Abstract
Dual rail logic is considered as a relevant hardware countermeasure against Differential Power Analysis (DPA) by making power consumption data independent. In this paper, we deduce from a thorough analysis of the robustness of dual rail logic against DPA the design range in which it can be considered as effectively robust. Surprisingly this secure design range is quite narrow. We therefore propose the use of an improved logic, called Secure Triple Track Logic, as an alternative to more conventional dual rail logics. To validate the claimed benefits of the logic introduced herein, we have implemented a sensitive block of the Data Encryption Standard algorithm (DES) and carried out by simulation DPA attacks.
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References
Kocher, P., et al.: Differential power analysis. In: Wiener, M.J. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 388–397. Springer, Heidelberg (1999)
Suzuki, et al.: Random Switching Logic: A Countermeasure against DPA based on Transition Probability, Cryptology ePrint Archive, report 2004/346
Bystrov, A., Yakovlev, A., Sokolov, D., Murphy, J.: Design and Analysis of Dual-Rail Circuits for Security Applications. IEEE Trans. on Computers 54(4), 449–460 (2005)
Guilley, S., et al.: CMOS Structures Suitable for Secure Hardware. In: 2004 Design, Automation and Test in Europe Conf. and Exposition (DATE 2004),February 2004, France, 16-20 (2004)
Fournier, J.J.A., et al.: Security Evaluation of Asynchronous Circuits. In: D.Walter, C., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 137–151. Springer, Heidelberg (2003)
Bouesse, G.F., et al.: DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement. In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March, 2005, Munich, Germany (2005)
Razafindraibe, A., et al.: Secure structures for secure asynchronous QDI circuits. In: DCIS 2004: 19th International Conference on Design of Circuits and Integrated Systems (DCIS 2004), November 24-26, 2004, Bordeaux, France (2004)
Tiri, K., et al.: Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology. In: D.Walter, C., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 125–136. Springer, Heidelberg (2003)
Tiri, K., et al.: A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs. In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March, 2005, Munich, Germany (2005)
Mace, F., et al.: A dynamic current mode logic to counteract power analysis attacks. In: DCIS 2004: 19th International Conference on Design of Circuits and Integrated Systems (DCIS 2004), November 24-26, 2004, Bordeaux, France (2004)
Maurine, P., et al.: Transition time modeling in deep submicron CMOS. IEEE Trans. on Computer Aided Design 21, 1352–1363 (2002)
Razafindraibe, A., et al.: Asynchronous Dual rail Cells to Secure Cryptosystem against Side Channel Attacks (SAME 2005), October 5-6, 2005, Sophia Antipolis, France (2005)
Maurine, P., et al.: Static Implementation of QDI Asynchronous Primitives. In: Chico, J.J., Macii, E. (eds.) PATMOS 2003. LNCS, vol. 2799, pp. 181–191. Springer, Heidelberg (2003)
Chaterzigeorgiou, A., et al.: Collapsing the Transistor Chain to an Effective Single Equivalent Transistor. In: 1998 Design Automation and Test in Europe (DATE 1998), February 23-26, 1998, Le Palais des Congres de Paris, Paris, France (1998)
http://www.cadence.com/products/digital_ic/soc_encounter/index.aspx
Piguet, C., et al.: Electrical Design of Dynamic and Static Speed Independent CMOS Circuits from Signal Transistion Graphs. In: 8th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 1998), Technical University of Denmark, October 7-9, 1998, pp. 357–366 (1998)
Kulikowski, K.J., et al.: Delay Insensitive Encoding and Power Analysis: A Balancing Act. In: 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2005), New York City, USA, March 13-16, 2005, pp. 116–125 (2005)
National Bureau of Standards: Data Encryption Standard, Federal Information Processing Standards Publication, vol. 46 (January 1977)
Eldo User’s Manual, Mentor Graphic’s Corp (1998)
Meng, T.H.-Y., et al.: Automatic Synthesis of Asynchronous Circuits from High-Level Specifications. IEEE Trans. On Computer Aided Design 8(11) (November 1989)
Razafindraibe, A., Robert, M., Renaudin, M., Maurine, P.: Evaluation of the robustness of dual rail logic against DPA. In: IEEE International Conference on Integrated Circuit Design and Technology (24-26 May, 2006)
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Razafindraibe, A., Robert, M., Maurine, P. (2007). Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA. In: Azémard, N., Svensson, L. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2007. Lecture Notes in Computer Science, vol 4644. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74442-9_33
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DOI: https://doi.org/10.1007/978-3-540-74442-9_33
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