Abstract
In this paper, we present a new efficient methodology for power estimation of the well known family of asynchronous circuits, QDI circuits, at pre-synthesized level. Power estimation at high-level is performed by simulating the intermediate format of the design. This format consists of concurrent processes represented with CSP-Verilog. The number of Reads and Writes accesses on the ports of these concurrent processes are counted by analyzing the conditional and computational portion during the simulation which is the based of our estimation methodology. To verify the accuracy of our presented method we applied it to a Reed-Solomon decoder as the benchmark. The results show up to 15 % imprecision in comparison with the power measured by SPICE, also simulation speed is faster by factor of 7 compared to gate-level transition counting based methodology.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Sparso, J., Furber, S.: Principles of Asynchronous Circuit Design – A System Perspective. Kluwer Academic Publishers, Dordrecht (2002)
Wong, C G., Martin, A.J.: High-Level Synthesis of Asynchronous Systems by Data Driven Decomposition. In: Proc. Of 40th DAC, June 2003, Anneheim, CA, USA (2003)
Martin, A.J.: Synthesis of Asynchronous VLSI Circuits Caltech, CS-TR-93-28 (1991)
Wong, C.G., Martin, A.J.: Data-Driven Process Decomposition for the Synthesis of Asynchronous circuits. In: Proc. ICECS (2001)
Lines, A.M.: Pipelined Asynchronous circuits" MSc Thesis, California Institute of Technology, June 1995 (revised 1998)
Martin, A.J.: Programming in VLSI, from Communicating Processes to Delay Insensitive Circuits. In: Hoare, C.A.R. (ed.) Developments in concurrency and communication, UT Year of programming Series, Addision Wesley, London (1990)
Singh, A., Smith, S.C.: Using a VHDL Testbench for Transistor-Level Simulation and Energy Calculation. In: The 2005 International Conference on Computer Design (2005)
Persia Site: http://www.async.ir/persia/persia.php
Seifhashemi, A., Pedram, H.: Verilog HDL, Powered by PLI: a Suitable Framework for Describing and Modeling Asynchronous Circuits at All Levels of Abstraction. In: Proc. Of 40th DAC, June 2003, Anneheim, CA, SA (2003)
Penzes, P.I., Martin, A.J.: An Energy Estimation Method for Asynchronous Circuits with Application to an Asynchronous Microprocessor. In: DATE Conference, Le Palais des Congres, Paris, France (2002)
Kudva, P., Akella, V.: A Technique for Estimating Power in Asynchronous Circuits. In: Proc. 1st International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), Salt lake city, Utah, pp. 166–175. IEEE Computer Society Press, Los Alamitos (1994)
Salehi, M., Saleh, K., Kalantari, H., Naderi, M., Pedram, H.: High level Energy Estimation of Template-Based QDI Asynchronous circuits Based on Transition Counting. In: ICM 2004, Tunis, Tunisia (2004)
Cortadella, J., Kondratyev, A., Kishinevsky, M., Lavagno, L., Yakovlev, A.V.: Petrify: A Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Systems (DCIS 1996), November 1996, Barcelona, pp. 205–210 (1996)
Beerel, P.A., Hsieh, C.-T., Wadekar, S.: Estimation of Energy Consumption in Speed-Independent Control Circuits. IEEE Transactions on CAD, 672–680 (June 1996)
Lee, I., Kim, H., Yang, P., Yoo, S., Chung, E.Y., Choi, K.-M., Kong, J.-T., Eo, S.-K.: Power Vip: SOC Power Estimation Framework at Transaction Level. In: Design Automation, Asia and South Pacific Conference (January 2006)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2007 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Ghavami, B., Niknahad, M., Najibi, M., Pedram, H. (2007). A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits. In: Azémard, N., Svensson, L. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2007. Lecture Notes in Computer Science, vol 4644. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74442-9_45
Download citation
DOI: https://doi.org/10.1007/978-3-540-74442-9_45
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-74441-2
Online ISBN: 978-3-540-74442-9
eBook Packages: Computer ScienceComputer Science (R0)