Abstract Modeling and Formal Verification of Microprocessors

Abstract

Moore’s Law continues to drive a severe increase in the number of transistors that can be integrated onto a single microprocessor chip. Computer architects and designers continue to look for ways to take advantage from it to produce ever more complex microprocessors. Meanwhile, market forces are dictating a shorter time to market, a proliferation of product and steeper volume ramps in production. However, it is evident that logic correctness is one of the main challenges that computer engineers usually face during the design and validation of such systems.

In the last 20 years, researchers and industrial experts invented several modeling and validation technologies, such as logic simulation, fast hardware emulation engines, and formal methods. However the design size and complexity continue to grow and outstrip what the validation techniques can do for producing high quality and correct systems. As a results, the validation problem is becoming more complex to solve and is indeed the main limiter for producing a high quality silicon products.

Design abstraction and high level modeling is a fundamental design strategy to cope with system complexity. The basic idea is to hide design implementation details, while focusing on design specification, capturing the pure logic properties and behaviors of the system. Doing this, we believe that the size of the design model can be dramatically decreased because none functional or physical properties of the design are excluded. Therefore the design representation is purely logical and have a clear semantics which it becomes easier to understand, easier and faster to validate using dynamic or formal techniques, so design errors can be detected earlier before going into detailed implementation and thus avoid a costly design iterations due to late soundness issues.

In this talk we will present abstract modeling techniques and their verification challenges. In particular we will describe the Abstract State Machines approach for modeling and verification of high level models. In addition we will outline several research topics in this domain to encourage the academic community to take an active part in exploring and developing new verification methods that can cope with the increasing complexity of microprocessors’ design.