Abstract
The continuous advances and progress made in hardware technologies makes it possible to foresee a realm of unprecedented performance levels and of new application-driven architectural designs, e. g., see [1]. One of the main drivers is the reduction of the size of the elementary devices. Nevertheless, the evolution of nanoscale technologies raises serious challenges with respect to both dependability and security viewpoints. Issues at stake encompass three main types of concerns i) unreliability and variability that will characterize the production of emerging nanoscale devices, ii) accidental disturbances that affect the operation of the systems, iii) malicious threats targeting vulnerabilities of hardware circuits. However, on the other hand, thanks to the large scale integration, one may expect the fault tolerance techniques to come to the rescue of the limitations of the currently dominating fault avoidance approaches. After a brief review of each of these issues, we will provide a few hints concerning a proposal for resilient multicore processor chips.
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Arlat, J. (2007). Nanoscale Technologies: Prospect or Hazard to Dependable and Secure Computing?. In: Bondavalli, A., Brasileiro, F., Rajsbaum, S. (eds) Dependable Computing. LADC 2007. Lecture Notes in Computer Science, vol 4746. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-75294-3_2
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DOI: https://doi.org/10.1007/978-3-540-75294-3_2
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