Skip to main content

Reducing Test Sequence Length Using Invertible Sequences

  • Conference paper
Formal Methods and Software Engineering (ICFEM 2007)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 4789))

Included in the following conference series:

Abstract

Conformance testing has been extensively studied in the context where the desired behavior of the implementation under test is modeled in terms of finite state machines. An essential issue in FSM-based conformance testing is to generate from a given finite state machine a test sequence that is both effective in detecting the faults in the implementation under test and efficient in terms of its length. In this paper, we consider test sequences satisfying the test criterion of the U-method as they have been proved to have high fault detectability. We present our solution to reduce the length of such a test sequence by maximizing the overlap among the test segments through the use of invertible sequences.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Naito, S., Tsunoyama, M.: Fault detection for sequential machines by transition tours. In: Proc. of 11th IEEE Fault Tolerant Computing Symposium, pp. 238–243. IEEE Computer Society Press, Los Alamitos (1981)

    Google Scholar 

  2. Aho, A.V., Dahbura, A., Lee, D., Uyar, M.: An optimization technique for protocol conformance test generation based on UIO sequences and Rural Chinese Postman Tours. IEEE Trans. Comm. 39(11), 1604–1615 (1991)

    Article  Google Scholar 

  3. Miller, R.E., Paul, S.: On the generation of minimal length conformance tests for communications protocols. IEEE/ACM Transactions on Networking 1(1), 116–129 (1993)

    Article  Google Scholar 

  4. Sabnani, K.K., Dahbura, A.: A protocol test generation procedure. Computer Networks and ISDN Systems 4(15), 285–297 (1988)

    Article  Google Scholar 

  5. Gonenc, G.: A method for the design of fault detection experiments. IEEE Trans. Computers 19(6), 551–558 (1970)

    Article  Google Scholar 

  6. Hennie, F.C.: Fault detecting experiments for sequential circuits. In: Proc. of 5th Ann. Symp. Switching Circuit Theory and Logical Design, pp. 95–110 (1964)

    Google Scholar 

  7. Ural, H., Wu, X., Zhang, F.: On minimizing the lengths of checking sequences. IEEE Transactions on Computers 46(1), 93–99 (1997)

    Article  Google Scholar 

  8. Chow, T.S.: Testing software design modeled by finite-state machines. IEEE Trans. Software Eng. SE-4(3), 178–187 (1978)

    Article  Google Scholar 

  9. Lai, R.: A survey of communication protocol testing. Journal of Systems and Software 62, 21–46 (2002)

    Article  Google Scholar 

  10. Lee, D., Yannakakis, M.: Principles and methods of testing finite state machines — a survey. Proceedings of The IEEE 84(8), 1090–1123 (1996)

    Article  Google Scholar 

  11. Sidhu, D.P., Leung, T.K.: Formal methods for protocol testing: A detailed study. IEEE Transactions on Software Engineering 15(4), 413–426 (1989)

    Article  Google Scholar 

  12. Motteler, H., Chung, A., Sidhu, D.: Fault coverage of UIO-based methods for protocol testing. In: Proc. of IFIP TC6/WG6.1 6th International Workshop on Protocol Test Systems, pp. 21–33 (1994)

    Google Scholar 

  13. Chen, J., Duan, L.: Conditions for avoiding controllability problems in distributed testing. In: Liu, Z., He, J. (eds.) ICFEM 2006. LNCS, vol. 4260, pp. 460–477. Springer, Heidelberg (2006)

    Chapter  Google Scholar 

  14. Hierons, R.M.: Extending test sequence overlap by invertibility. The Computer Journal 39(4), 325–330 (1996)

    Article  Google Scholar 

  15. Hierons, R.M.: Testing from a finite state machine: extending invertibility to sequences. The Computer Journal 40(4), 220–230 (1997)

    Article  Google Scholar 

  16. Yang, B., Ural, H.: Protocol conformance test generation using multiple UIO sequence with overlapping. In: ACM SIGCOMM 1990, pp. 118–125. ACM Press, New York (1990)

    Chapter  Google Scholar 

  17. Chen, J., Hierons, R.M., Ural, H., Yenigun, H.: Eliminating redundant tests in a checking sequence. In: Khendek, F., Dssouli, R. (eds.) TestCom 2005. LNCS, vol. 3502, pp. 146–158. Springer, Heidelberg (2005)

    Google Scholar 

  18. Hierons, R.M., Ural, H.: Reduced length checking sequences. IEEE Transactions on Computers 51(9), 1111–1117 (2002)

    Article  MathSciNet  Google Scholar 

  19. Tekle, K.T., Ural, H., Yalcin, M.C., Yenigun, H.: Generalizing redundancy elimination in checking sequences. In: Yolum, p., Güngör, T., Gürgen, F., Özturan, C. (eds.) ISCIS 2005. LNCS, vol. 3733, pp. 915–926. Springer, Heidelberg (2005)

    Chapter  Google Scholar 

  20. Eiselt, H.A., Gendreau, M., Laporte, G.: Arc routing problems, part II: the Rural Postman Problem. Operations Research 43, 399–414 (1995)

    Article  MATH  MathSciNet  Google Scholar 

  21. Hierons, R.M.: Testing from a non-deterministic finite state machine using adaptive state counting. IEEE Transactions on Computers 53(10), 1330–1342 (2004)

    Article  Google Scholar 

  22. Luo, G., Bochmann, G., Petrenko, A.: Test selection based on communicating nondeterministic finite state machines using a generalized Wp-method. IEEE Transactions on Software Engineering 20, 149–162 (1994)

    Article  Google Scholar 

  23. Tretmans, J.: Conformance testing with labelled transition systems: Implementation relation and test generation. Computer Networks and ISDN Systems 29, 49–79 (1996)

    Article  Google Scholar 

  24. Ammann, P.E., Black, P.E., Majurski, W.: Using model checking to generate tests from specifications. In: ICFEM 1998, pp. 46–54. IEEE Computer Society Press, Los Alamitos (1998)

    Google Scholar 

  25. Vries, R.d., Tretmans, J.: On-the-fly conformance testing using SPIN. International Journal on Software Tools for Technology Transfer 2(4), 382–393 (2000)

    Article  MATH  Google Scholar 

  26. Hong, H.S., Ural, H.: Using model checking for reducing the cost of test generation. In: Grabowski, J., Nielsen, B. (eds.) FATES 2004. LNCS, vol. 3395, pp. 110–124. Springer, Heidelberg (2005)

    Google Scholar 

  27. Sarikaya, B., Bochmann, G.V.: Synchronization and specification issues in protocol testing. IEEE Transactions on Communications 32, 389–395 (1984)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Michael Butler Michael G. Hinchey María M. Larrondo-Petrie

Rights and permissions

Reprints and permissions

Copyright information

© 2007 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Duan, L., Chen, J. (2007). Reducing Test Sequence Length Using Invertible Sequences. In: Butler, M., Hinchey, M.G., Larrondo-Petrie, M.M. (eds) Formal Methods and Software Engineering. ICFEM 2007. Lecture Notes in Computer Science, vol 4789. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-76650-6_11

Download citation

  • DOI: https://doi.org/10.1007/978-3-540-76650-6_11

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-76648-3

  • Online ISBN: 978-3-540-76650-6

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics