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The Design on SEU-Tolerant Information Processing System of the On-Board-Computer

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Advanced Parallel Processing Technologies (APPT 2007)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 4847))

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Abstract

For SEU(Single-Event-Upsets) of space radiation environment, a multi-level fault-tolerant mechanism based-on FPGA, which has greatly improved the system’s ability of resisting SEU was presented. The design of three-level fault-tolerant included the dual fault-tolerant system based-on FPGA, the module-level triple modular redundancy, and the chip-level SEU-tolerant FPGA. Finally, the evaluation for the SEU reliability of the OBC(on-board-computer) was mentioned.

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References

  1. Du, W., Tan, W.: Research on Realizationof ASIC in Chinese Spacecraft. Chinese Space Science and Technology 5 (2002)

    Google Scholar 

  2. Reorda, S., Paccagnella, A.: Analyzing SEU Effects in SRAM-based FPGAs. IOLTS2003: IEEE International On-Line Testing Symposium , 119–123 (2003)

    Google Scholar 

  3. Pratt, B., Johnson, E., Wirthlin, M., Caffrey, M., Morgan, K., Graham, P.: Improving FPGA Design Robustness with Partial TMR. In: MAPLD 2005, Washington, D.C. (September 2005)

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  4. Lai, A.: Mitigation techniques for electronics in Single Event Upset environments[EB/OL]. US: Opensystems Publishing, Military Embedded Systems, [2006-6-27]. (2006), http://www.mil-embeded.com/articles/authors/lai

  5. Xiang, L., Qu, G.: The Fault Tolerant System Design of Housekeeping Computer for small satellite. Aerospace Control 2, 92–96 (2005)

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Ming Xu Yinwei Zhan Jiannong Cao Yijun Liu

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© 2007 Springer-Verlag Berlin Heidelberg

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Ying, H., Chun-yuan, Z., Dong, L., Yi, L., Sheng-xin, W. (2007). The Design on SEU-Tolerant Information Processing System of the On-Board-Computer. In: Xu, M., Zhan, Y., Cao, J., Liu, Y. (eds) Advanced Parallel Processing Technologies. APPT 2007. Lecture Notes in Computer Science, vol 4847. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-76837-1_7

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  • DOI: https://doi.org/10.1007/978-3-540-76837-1_7

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-76836-4

  • Online ISBN: 978-3-540-76837-1

  • eBook Packages: Computer ScienceComputer Science (R0)

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