Abstract
As feature size shrinks, the dominant component of power consumption will be leakage. As caches represent a considerable fraction of area for many platforms, from embedded to highly paralleled systems, cache leakage control continues to become a critical issue. Drowsy cache technique is a state-preserving technique which reduces leakage by pulling down the voltages on selected lines. To exploit the temporal locality present in the data stream, existing drowsy cache policies update drowsy/active mode after an execution window of fixed clock cycles, which lack the flexibility to adapt to program behavior. We introduce a tri-mode FSM control policy, which exploits global Reuse Distance information and tries to keep a small set of lines in active for future references, after each N distinct line references. This Reuse Distance based policy well adapts to the temporal locality, steadily delivers better energy savings with similar performance overhead, is simple to implement, and places an upper bound on leakage power.
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References
Flautner, K., Kim, N., Martin, S., Blaauw, D., Mudge, T.: Drowsy caches: Simple techniques for reducing leakage power. In: Proc.29th IEEE/ACM International Symposium on Computer Architecture, pp. 529–551. New York (2002)
Doyle, B., Arghavani, R., Barlage, D., Datta, S., Doczy, M., Kavalieros, J., Murthy, A., Chau, R.: Transistor elements for 30nm physical gate lengths and beyond. Intel Journal. J. 6, 42–54 (2002)
Puri, R., Stok, L., Bhattacharya, S.: Keeping hot chips cool. In: Proceedings of the 42th DAC, pp. 285–288 (2005)
Kim, N., Flautner, K., Blaauw, D., Mudge, T.: Drowsy instruction caches: Leakage power reduction using dynamic voltage scaling and cache sub-bank prediction. In: Proc.36th IEEE/ACM International Symposium on Microarchitecture, pp. 219–230 (2002)
Petit, S., Sahuquillo, J., Such, J., Kaeli, D.: Exploiting temporal locality in drowsy cache policies. In: Proc. ACM Computing Frontiers Conference, pp. 371–377 (2005)
Powell, M., Yang, S.H., Falsafi, B., Roy, K., Vijaykumar, T.: Gated-Vdd: A circuit technique to reduce leakage in deep-submicron cache memories. In: Proc. IEEE/ACM International Symposium on Low Power Electronics and Design, pp. 90–95 (2000)
Kaxiras, S., Hu, Z., Martonosi, M.: Cache decay: Exploiting generational behavior to reduce cache leakage power. In: Proc. 36th IEEE/ACM International Symposium on Computer Architecture, pp. 240–251 (2001)
Huiyang, Z., Toburen, M.C., Rotenberg, E., Conte, T.M.: Adaptive mode control: A static-power-efficient cache design. In: Proc. 10th IEEE International Symposium on Parallel Architectures and Compilation Techniques, pp. 61–70 (2001)
Abella, J., et al.: IATAC: A smart predictor to turn-off L2 cache lines. ACM Transactions on Architecture and Code Optimization 2, 55–77 (2005)
Sherwood, T., Perelman, E., Hamerly, G., Calder, B.: Automatically characterizing large scale program behavior. In: Proc. 10th ACM Symposium on Architectural Support for Programming Languages and Operating Systems, pp. 45–57 (2002)
Sharkey, J.: M-Sim: A flexible, multi-threaded simulation environment. Technical Report CS-TR-05-DP1, Dept. of CS, SUNY Binghamton (2005)
Zhang, Y., Parikh, D., Sankaranarayanan, K., Skadron, K., Stan, M.: Hotleakage: A temperature-aware model of subthreshold and gate leakage for architects. Technical Report CS-2003-05. Dept. of CS, University of Virginia (2003)
Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A framework for architectural-level power analysis and optimizations. In: Proc. 27th IEEE/ACM International Symposium on Computer Architecture, pp. 83–94 (2000)
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© 2007 Springer-Verlag Berlin Heidelberg
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Zhao, Y., Li, X., Tong, D., Cheng, X. (2007). Reuse Distance Based Cache Leakage Control. In: Aluru, S., Parashar, M., Badrinath, R., Prasanna, V.K. (eds) High Performance Computing – HiPC 2007. HiPC 2007. Lecture Notes in Computer Science, vol 4873. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-77220-0_34
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DOI: https://doi.org/10.1007/978-3-540-77220-0_34
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