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Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions

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High Performance Embedded Architectures and Compilers (HiPEAC 2008)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 4917))

Abstract

This paper describes the development and compiler utilization of variable length instruction set extensions to an existing high-performance, 32-bit VLIW DSP processor. We describe how the instruction set extensions (1) reduce code size significantly, (2) are binary compatibile with older object code, (3) do not require the processor to switch “modes”, and (4) are exploited by a compiler. We describe the compiler strategies that utilize the new instruction set extensions to reduced code size. When compiling our benchmark suite for best performance, we show that our compiler uses the variable length instructions to decreases code size by 11.5 percent, with no reduction in performance. We also show that our implementation allows a wider code size and performance tradeoff range than earlier versions of the architecture.

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References

  1. Rau, B.R., Fisher, J.A.: Instruction-level parallel processing: History, overview, and perspective. Journal of Supercomputing 7(1-2), 9–50 (1993)

    Article  Google Scholar 

  2. Conte, T.M., Banerjia, S., Larin, S.Y., Menezes, K.N., Sathaye, S.W.: Instruction fetch mechanisms for VLIW architectures with compressed encodings. In: MICRO 29: Proceedings of the 29th annual ACM/IEEE International Symposium on Microarchitecture, pp. 201–211. IEEE Computer Society, Washington, DC, USA (1996)

    Chapter  Google Scholar 

  3. Lin, C.H., Xie, Y., Wolf, W.: LZW-based code compression for VLIW embedded systems. In: DATE 2004. Proceedings of the Conference on Design, Automation and Test in Europe, vol. 3, pp. 76–81. IEEE Computer Society Press, Washington, DC, USA (2004)

    Google Scholar 

  4. Ros, M., Sutton, P.: Compiler optimization and ordering effects on VLIW code compression. In: CASES 2003. Proceedings of the 2003 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, pp. 95–103. ACM Press, New York (2003)

    Chapter  Google Scholar 

  5. Aditya, S., Mahlke, S.A., Rau, B.R.: Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats. ACM Transactions on Design Automation of Electronic Systems 5(4), 752–773 (2000)

    Article  Google Scholar 

  6. ARM Limited: ARM7TDMI (Rev. 4) Technical Reference Manual (2001)

    Google Scholar 

  7. Phelan, R.: Improving ARM code density and performance. Technical report, ARM Limited (2003)

    Google Scholar 

  8. MIPS Technologies: MIPS32 Architecture for Programmers, Vol. IV-a: The MIPS16 Application Specific Extension to the MIPS32 Architecture (2001)

    Google Scholar 

  9. Texas Instruments: TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide, Literature number spru732c (2006)

    Google Scholar 

  10. Stotzer, E., Leiss, E.: Modulo scheduling for the TMS320C6x VLIW DSP architecture. In: LCTES 1999. Proceedings of the ACM SIGPLAN 1999 Workshop on Languages, Compilers, and Tools for Embedded Systems, pp. 28–34. ACM Press, New York (1999)

    Chapter  Google Scholar 

  11. Briggs, P., Cooper, K.D., Torczon, L.: Improvements to graph coloring register allocation. ACM Transactions on Programming Languages and Systems 16(3), 428–455 (1994)

    Article  Google Scholar 

  12. Davis, A.L., Humphreys, J.F., Tatge, R.E.: Maintaining code consistency among plural instruction sets via function naming convention, U.S. Patent 6,002,876 (1999)

    Google Scholar 

  13. Texas Instruments: TMS320C6000 Optimizing Compiler User’s Guide, Literature number spru187 (2000)

    Google Scholar 

  14. Merten, M.C., Hwu, W.W.: Modulo schedule buffers. In: MICRO 34: Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, pp. 138–149. IEEE Computer Society, Washington, DC, USA (2001)

    Chapter  Google Scholar 

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Per Stenström Michel Dubois Manolis Katevenis Rajiv Gupta Theo Ungerer

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© 2008 Springer-Verlag Berlin Heidelberg

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Hahn, T.T., Stotzer, E., Sule, D., Asal, M. (2008). Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions. In: Stenström, P., Dubois, M., Katevenis, M., Gupta, R., Ungerer, T. (eds) High Performance Embedded Architectures and Compilers. HiPEAC 2008. Lecture Notes in Computer Science, vol 4917. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-77560-7_11

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  • DOI: https://doi.org/10.1007/978-3-540-77560-7_11

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-77559-1

  • Online ISBN: 978-3-540-77560-7

  • eBook Packages: Computer ScienceComputer Science (R0)

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