Abstract
Modern mobile devices need to be extremely energy efficient. Due to the growing complexity of these devices, energy aware design exploration has become increasingly important. Current exploration tools often do not support energy estimation, or require the design to be very detailed before the estimate is possible. It is important to get early feedback on both performance and energy consumption during all phases of the design and at higher abstraction levels. This paper presents a unified optimization and exploration framework, from source level transformation to processor architecture design. The proposed retargetable compiler and simulator framework can map applications to a range of processors and memory configurations, simulate and report detailed performance and energy estimates. An accurate energy modeling approach is introduced, which can estimate the energy consumption of processor and memories at a component level, which can help to guide the design process. Fast energy-aware architecture exploration is illustrated using an example processor. The flow is demonstrated using a representative wireless benchmark on two state of the art processors and on a processor with advanced low power extensions for memories. The framework also supports exploration of various novel low power extensions and their combinations. We show that a unified framework enables fast feedback on the effect of source level transformations of the application code on the final cycle count and energy consumption.
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References
Trimaran: An Infrastructure for Research in Instruction-Level Parallelism (1999), http://www.trimaran.org
Austin, T., Larson, E., Ernst, D.: Simplescalar: an infrastructure for computer system modeling. IEE Computer Magazine 35(2), 59–67 (2002)
Ascia, G., Catania, V., Palesi, M., Patti, D.: Epic-explorer: A parameterized VLIW-based platform framework for design space exploration. In: Proc of ESTIMedia, pp. 3–4 (2003)
Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A framework for architectural-level power analysis and optimizations. In: Proc of ISCA, pp. 83–94 (June 2000)
SUIF2 Compiler System (2001), http://suif.stanford.edu
Cohen, A., Sigler, M., Girbal, S., Temam, O., Parello, D., Vasilache, N.: Facilitating the search for compositions of program transformations. In: Proc of ICS, pp. 151–160 (2005)
Gordon-Ross, A., Cotterell, S., Vahid, F.: Exploiting fixed programs in embedded systems: A loop cache example. In: Proc of IEEE Computer Architecture Letters (January 2002)
Jayapala, M., Barat, F., Vander Aa, T., Catthoor, F., Corporaal, H., Deconinck, G.: Clustered loop buffer organization for low energy VLIW embedded processors. IEEE Transactions on Computers 54(6), 672–683 (2005)
Starcore DSP Techology, SC140 DSP Core Reference Manual (June 2000), http://www.starcore-dsp.com
Texas Instruments, Inc. TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (May 2006), http://focus.ti.com/docs/apps/catalog/resources/appnoteabstract.jhtmlabstractName=spru732b
Vander Aa, T., Jayapala, M., Barat, F., Deconinck, G., Lauwereins, R., Catthoor, F., Corporaal, H.: Instruction buffering exploration for low energy VLIWs with instruction clusters. In: Proc. of ASPDAC 2004, Yokohama, Japan (January 2004)
Raghavan, P., Lambrechts, A., Jayapala, M., Catthoor, F., Verkest, D.: Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors. In: Proc of DATE (2006)
Schuster, T., Bougard, B., Raghavan, P., Priewasser, R., Novo, D., Vanderperre, L., Catthoor, F.: Design of a low power pre-synchronization asip for multimode sdr terminals. In: Proc. of SAMOS (2007)
Baron, M.: Cortex a8:high speed, low power. In Microprocessor Report (October 2005)
Rixner, S., Dally, W.J., Khailany, B., Mattson, P.R., Kapasi, U.J., Owens, J.D.: Register organization for media processing. In: HPCA, pp. 375–386 (January 2000)
Gangawar, A., Balakrishnan, M., Kumar, A.: Impact of intercluster communication mechanisms on ilp in clustered VLIW architectures. In: ACM TODAES, pp. 1–29 (2007)
Girbal, S., Vasilache, N., Bastoul, C., Cohen, A., Parello, D., Sigler, M., Temam, O.: Semi-automatic composition of loop transformations for deep parallelism and memory hierarchies. International Journal of Parallel Programming, 261–317 (October 2006)
Faraday Technology, Corporation Faraday UMC 90nm RVT Standard Cell Library (2007), http://www.faraday-tech.com
Synopsys, Inc. Design Compiler User Guide (2006)
Cadence, Inc. Cadence SoC Encounter User Guide (2006)
Synopsys, Inc. Prime Power User Guide (2006)
Holma, H., Toskala, A.: WCDMA for UMTS: Radio Access for Third Generation Mobile Communications. John Wiley, Chichester (2001)
Lin, Y., Lee, H., Woh, M., Harel, Y., Mahlke, S., Mudge, T., Chakrabarti, C., Flautner, K.: SODA: A low-power architecture for software radio. In: Proc of ISCA (2006)
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Raghavan, P., Lambrechts, A., Absar, J., Jayapala, M., Catthoor, F., Verkest, D. (2008). Coffee: COmpiler Framework for Energy-Aware Exploration. In: Stenström, P., Dubois, M., Katevenis, M., Gupta, R., Ungerer, T. (eds) High Performance Embedded Architectures and Compilers. HiPEAC 2008. Lecture Notes in Computer Science, vol 4917. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-77560-7_14
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DOI: https://doi.org/10.1007/978-3-540-77560-7_14
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-77559-1
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