Abstract
Simultaneous multithreading (SMT) processors might be good candidates to fulfill the ever increasing performance requirements of embedded applications. However, state-of-the-art SMT architectures do not exhibit enough timing predictability to allow a static analysis of Worst-Case Execution Times. In this paper, we analyze the predictability of various policies implemented in SMT cores to control the sharing of resources by concurrent threads. Then, we propose an SMT architecture designed to run one hard real-time thread so that its execution time is analyzable even when other (non critical) threads are executed concurrently. Experimental results show that this architecture still provides high mean and worst-case performance.
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Barre, J., Rochange, C., Sainrat, P. (2008). A Predictable Simultaneous Multithreading Scheme for Hard Real-Time. In: Brinkschulte, U., Ungerer, T., Hochberger, C., Spallek, R.G. (eds) Architecture of Computing Systems – ARCS 2008. ARCS 2008. Lecture Notes in Computer Science, vol 4934. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-78153-0_13
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DOI: https://doi.org/10.1007/978-3-540-78153-0_13
Publisher Name: Springer, Berlin, Heidelberg
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