Abstract
Task preemption is a critical mechanism for building an effective multitasking environment on dynamically reconfigurable processors. When being preempted, necessary state information of the interrupted task in registers and distributed internal memories must be correctly preserved. This paper aims at studying a method for saving and restoring the state data of a hardware task, executing on a dynamically reconfigurable processing array, taking into account the great amount and the distribution on different storage elements of data. Performance degradation caused by task preemption is minimized by allowing preemption only at predefined points where demanded resources are small. Specifically, we propose: 1) algorithms to insert preemption points subject to user-specified preemption latency and resource overhead constraints; 2) modification steps to incorporate the offered algorithms on the system design flow. Evaluation results on the NEC DRP architecture show that the proposed method achieves a reasonable hardware overhead (from 6% to 14%) while satisfying a given preemption latency.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Kim, K., Karri, R., Potkonjak, M.: Micropreemption Synthesis: An Enabling Mechanism for Multitask VLSI Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25(1), 19–30 (2006)
Jean, J.S.N., Tomko, K., Yavagal, V., Shah, J., Cook, R.: Dynamic reconfiguration to support concurrent applications. IEEE Trans. on Computers 48(6), 591–602 (1999)
Brebner, G.: The Swappable Logic Unit: A Paradigm for Virtual Hardware. In: IEEE Symposium on FPGAs for CCMs, pp. 77–86 (1997)
Simmler, H., Levinson, L., Manner, R.: Multitasking on FPGA Coprocessors. In: Proc. of the 10th International Workshop on FPGA, pp. 121–130 (2000)
Levinson, L., Männer, R., Sesler, M., Simmler, H.: Preemptive Multitasking on FPGAs. In: Proc. of the 2000 IEEE Symposium on FCCM (2000)
Guccione, S.A., Levi, D., Sundararajan, P.: JBits: A Java-based interface for reconfigurable computing. In: Proc. of Second Annual MAPLD (September 1999)
Kalte, H., Porrmann, M.: Context Saving and Restoring for Multitasking in Reconfigurable Systems. In: Proc. of 15th FPL, vol. 228, pp. 223–228 (August 2005)
Koch, D., Haubelt, C., Teich, J.: Efficient hardware checkpointing: concepts, overhead analysis, and implementation. In: Proc. of FPGA, pp. 188–196 (February 2007)
Jovanovic, S., Tanougast, C., Weber, S.: A Hardware Preemptive Multitasking Mechanism Based on Scan-path Register Structure for FPGA-based Reconfigurable Systems. In: Proc. of NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pp. 358–364 (August 2007)
Ullmann, M., Hübner, M., Grimm, B., Becker, J.: An FPGA Run-Time System for Dynamical On-Demand Reconfiguration. In: Proc. of 11th RAW (April 2004)
Motomura, M.: A Dynamically Reconfigurable Processor Architecture. Microprocessor Forum (October 2002)
Simonson, J., Patel, J.H.: Use of Preferred Preemption Points in Cache-Based Real-Time Systems. In: Proc. of International Computer Performance and Dependability Symposium, pp. 316–325 (April 1995)
Lee, E.A., Messerschmitt, D.C.: Static Scheduling of Synchronous Data flow Programs for Digital Signal Processing. IEEE Trans. on Computers 36(1), 24–36 (1987)
Aho, A.V., Sethi, R., Ullman, J.D.: Compiler: Principles, Techniques, and Tools. Addison-Wesley, Reading (1986)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2008 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Manh Tuan, V., Amano, H. (2008). A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor. In: Woods, R., Compton, K., Bouganis, C., Diniz, P.C. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2008. Lecture Notes in Computer Science, vol 4943. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-78610-8_18
Download citation
DOI: https://doi.org/10.1007/978-3-540-78610-8_18
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-78609-2
Online ISBN: 978-3-540-78610-8
eBook Packages: Computer ScienceComputer Science (R0)