Abstract
ARISE introduces a systematic approach to extend once a processor to support thereafter the coupling of an arbitrary number of Custom Computing Units (CCUs). A CCU, hardwired or reconfigurable, can be utilized in a hybrid, tight and/or loose, model of computation. By selecting the appropriate model for each part of the application, the complete application space can be considered for acceleration, resulting to significant performance improvements. To support these features ARISE proposes: i) a machine organization, ii) a set of Instruction Set Extensions (ISEs), and iii) a micro-architecture. To evaluate our proposal, a MIPS processor is extended with the ARISE infrastructure and implemented on an FPGA. Results show that the ARISE infrastructure can easily fit into the timing model of the processor. A set of benchmarks is mapped on the evaluation machine and it is proved that exploiting the hybrid model of computation, performance improvements of up to 68% are achieved compared to the case when only one model is supported. This results to significant application speedups from 2.4x up to 4.8x.
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Vassiliadis, N., Theodoridis, G., Nikolaidis, S. (2008). ARISE Machines: Extending Processors with Hybrid Accelerators. In: Woods, R., Compton, K., Bouganis, C., Diniz, P.C. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2008. Lecture Notes in Computer Science, vol 4943. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-78610-8_20
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DOI: https://doi.org/10.1007/978-3-540-78610-8_20
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