Advances in Automated Source-Level Debugging of Verilog Designs

Abstract

Developing models for fault localization in HDL designs has been an active research area in recent years. Whereas research on circuit verification is typically conducted on Verilog programs, research on fault localization has recently focused on the VHDL domain. The research presented herein focuses on fault localization models for Verilog designs and thus promotes the investigation of the relationships between models for property verification and fault localization. Primarily we focus on two novel contributions. First, this article points out notable semantic differences between VHDL and Verilog models and discusses its implications for fault localizations. Secondly, we advance existing work by incorporating multiple testcases and provide first empirical results obtained from the the ISCAS 89 benchmarks indicating our novel technique’s applicability for real world designs.