Abstract
In this paper, an evolutionary approach is used to design multiple constant multipliers (MCMs). As these circuits can be composed of adders, subtractors and shifters, they perform a linear transform. An important consequence is that only a single input value is sufficient to completely evaluate a candidate circuit independently of its size and the bit width of the datapath. Proposed method is able to compete with well-optimized heuristics in particular problem instances. This paper also deals with a hardware acceleration of the method in FPGA which provides the speedup of two orders of magnitude in comparison with a conventional PC.
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Vašíček, Z., Žádník, M., Sekanina, L., Tobola, J. (2008). On Evolutionary Synthesis of Linear Transforms in FPGA. In: Hornby, G.S., Sekanina, L., Haddow, P.C. (eds) Evolvable Systems: From Biology to Hardware. ICES 2008. Lecture Notes in Computer Science, vol 5216. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-85857-7_13
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DOI: https://doi.org/10.1007/978-3-540-85857-7_13
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