Abstract
As the size of CMOS devices is approaching the atomic level, the increasing intrinsic device variability is leading to higher failure rates in conventional CMOS designs. In this paper, two approaches are proposed for evolving unconventional variability-tolerent CMOS designs: one uses a simple Genetic Algorithm, whilst the other uses Cartesian Genetic Programming. Both approaches successfully evolve unconventional designs for logic gates, whilst an inverter design also shows signs of variability-tolerance.
The authors would like to thank all partners of the nano-CMOS project, especially the DMG at the University of Glasgow for their Randomspice program.
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Walker, J.A., Hilder, J.A., Tyrrell, A.M. (2008). Evolving Variability-Tolerant CMOS Designs. In: Hornby, G.S., Sekanina, L., Haddow, P.C. (eds) Evolvable Systems: From Biology to Hardware. ICES 2008. Lecture Notes in Computer Science, vol 5216. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-85857-7_27
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DOI: https://doi.org/10.1007/978-3-540-85857-7_27
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