Abstract
In this paper, a stepwise dimension reduction (SDR) approach to evolutionary design of relatively large combinational logic circuits is proposed. The proposed method divides the whole circuit into several layers. As for a circuit with one output, the number of input combinations is expected to be reduced layer-by-layer. The current layer’s outputs are the next layer’s inputs. All layers are evolved separately one after another, and assembled to form a final solution. The experimental results of SDR on parities, multipliers and circuits taken from MCNC library are comparable with those of GDD. Especially, the 19-parity circuit can be evolved successfully.
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Yao, X., Higuichi, T.: Promises and Challenges of Evolvable Hardware. IEEE Transactions On Systems Man and Cybernetics-Part C: Applications and Reviews 29(1), 87–97 (1999)
Stomeo, E., Kalganova, T., Lambert, C.: Generalized Disjunction Decomposition for Evolvable Hardware. IEEE Transactions on Systems, Man and Cybernetics, Part B 36(5), 1024–1043 (2006)
Miller, J., Job, D.: Principles in the Evolutionary Design of Digital Circuits - Part I. Genetic Programming and Evolvable Machines 1(1), 7–35 (2000)
Higuchi, T.: Evolvable Hardware and It’s Application to Pattern Recognition and Fault-Tolerant Systems. In: Sanchez, E., Tomassini, M. (eds.) Towards Evolvable Hardware 1995. LNCS, vol. 1062, pp. 118–135. Springer, Heidelberg (1996)
Schnier, T., Yao, X.: Using Negative Correlation to Evolve Fault-Tolerant Circuits. In: Tyrrell, A.M., Haddow, P.C., Torresen, J. (eds.) ICES 2003. LNCS, vol. 2606, pp. 213–220. Springer, Heidelberg (2003)
Vassilev, V., Miller, J.: Scalability Problems of Digital Circuit Evolution Evolvability and Efficient Designs. In: Proceedings of the Second NASA/DoD Workshop on Evolvable Hardware, pp. 55–64. IEEE, Los Alamitos (2000)
Gordon, T.G.W., Bentley, P.J.: Development Brings Scalability to Hardware Evolution. In: Proceedings of the 2005 NASA/DoD Conference on Evolvable Hardware (EH 2005), pp. 272–279. IEEE Computer Society Press, Los Alamitos (2005)
Sekanina, L.: Evolutionary Design of Digital Circuits: Where Are Current Limits? In: Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), Istanbul, Turkey, pp. 171–178. IEEE Computer Society, Los Alamitos (2006)
Torresen, J.: A Divide-and-Conquer Approach to Evolvable Hardware. In: Sipper, M., Mange, D., Pérez-Uribe, A. (eds.) ICES 1998. LNCS, vol. 1478, pp. 57–65. Springer, Heidelberg (1998)
Higuchi, T.: Evlovable Hardware at Function Level. In: Proceedings of 1997 IEEE International Conference on Evolutionary Computation (ICEC 1997), pp. 187–192 (1997)
Kalganova, T.: Bidirectional Incremental Evolution in Extrinsic Evolvable Hardware. In: Proceedings of the Second NASA/DoD Workshop on Evolvable Hardware (EH 2000), Palo Alto, CA, USA, pp. 65–74. IEEE Computer Society Press, Los Alamitos (2000)
Yang, S.: Logic Synthesis and Optimization. Benchmarks, Version 3.0, Microelectronics Center of North Carolina (1991)
Harik, G., Lobo, F., Goldberg, D.: The Compact Genetic Algorithm. IEEE Transactions on Evolutionary Computation 3(4), 287–297 (1999)
Sakanashi, H., Salami, M., Iwata, M., Nakaya, S., Yamauchi, T., Inuo, T., Kajihara, N., Higuchi, T.: Evolvable Hardware Chip for High Precision Printer Image Compression. In: The 15th National Conference on Artificial Intelligence, Madison, Wisconsin, pp. 486–491 (1998)
Koza, J.R.: Genetic Programming: On the Programming of Computers by Means of Natural Selection. MIT Press, Cambridge, MA (1992)
Araujo, S., Mesquita, A., Pedroza, A.: Using Genetic Programming and High Level Synthesis to Design Optimized Datapath. In: Tyrrell, A.M., Haddow, P.C., Torresen, J. (eds.) ICES 2003. LNCS, vol. 2606, pp. 434–445. Springer, Heidelberg (2003)
Bäck, T., Hoffmeister, F., Schwefel, H.P.: A Survey of Evolutionary Strategies. In: Proceedings of the 4th International Conference on Genetic Algorithms, San Francisco, CA, pp. 2–9 (1991)
Stomeo, E., Kalganova, T., Lambert, C.: On Evolution of Relatively Large Combinational Logic Circuits. In: Proceedings of 2005 NASA/DoD Conference on Evolvable Hardware, pp. 59–66. IEEE, Los Alamitos (2005)
Miller, T.: Cartesian Genetic Programming. In: Poli, R., Banzhaf, W., Langdon, W.B., Miller, J., Nordin, P., Fogarty, T.C. (eds.) EuroGP 2000. LNCS, vol. 1802, pp. 121–132. Springer, Heidelberg (2000)
Stomeo, E., Kalganova, T., Lambert, C.: A Novel Genetic Algorithm for Evolvable Hardware. In: Proceedings of the 2006 IEEE Congress on Evolutionary Computation, pp. 441–448. IEEE Computer Society Press, Canada (2006)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2008 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Li, Z., Luo, W., Wang, X. (2008). A Stepwise Dimension Reduction Approach to Evolutionary Design of Relative Large Combinational Logic Circuits. In: Hornby, G.S., Sekanina, L., Haddow, P.C. (eds) Evolvable Systems: From Biology to Hardware. ICES 2008. Lecture Notes in Computer Science, vol 5216. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-85857-7_5
Download citation
DOI: https://doi.org/10.1007/978-3-540-85857-7_5
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-85856-0
Online ISBN: 978-3-540-85857-7
eBook Packages: Computer ScienceComputer Science (R0)