Abstract
This paper presents a design for an efficient architecture of a reconfigurable bit-serial polynomial basis multiplier for Galois field GF(2m). The multiplier operates on the Most Significant Bit (MSB)-first for finite field multiplication. The design is flexible enough to configure different value of irreducible polynomial degree m for multiplication. Since the multiplier is doing a bit-serial processing with the gated clock technique, thus the design would be suitable for low power devices. Another advantage of the proposed architecture is the improvement of its maximum clock frequency and the high order of flexibility which allows an easy configuration for different field sizes.
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Nikooghadam, M., Malekian, E., Zakerolhosseini, A. (2008). A Versatile Reconfigurable Bit-Serial Multiplier Architecture in Finite Fields GF(2m). In: Sarbazi-Azad, H., Parhami, B., Miremadi, SG., Hessabi, S. (eds) Advances in Computer Science and Engineering. CSICC 2008. Communications in Computer and Information Science, vol 6. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-89985-3_28
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DOI: https://doi.org/10.1007/978-3-540-89985-3_28
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