Abstract
As contemporary digital systems specifically embedded systems become more and more complex, taking advantage of system-level design is being more widespread. Many embedded systems must operate under strict timing constraints. One of the best methods for examining timing constraints in an embedded system can be done via the performance verification. In this paper an assertion-based verification methodology has been proposed for verifying system-level timing constraints in an embedded system. Performance assertions are specified by an assertion language at the transaction-level of abstraction. A Turing machine and a structure named performance evaluator have been coupled to provide a computational model for a performance assertion. We have developed a tool that can automatically generate a C++ code from input assertions. The result code operates as the computational model and checks the assertions by applying a simulation-based trace analysis approach. Through a case study, we demonstrate usefulness and effectiveness of our methodology.
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Hatefi-Ardakani, H., Gharehbaghi, A.M., Hessabi, S. (2008). System-Level Assertion-Based Performance Verification for Embedded Systems. In: Sarbazi-Azad, H., Parhami, B., Miremadi, SG., Hessabi, S. (eds) Advances in Computer Science and Engineering. CSICC 2008. Communications in Computer and Information Science, vol 6. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-89985-3_30
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DOI: https://doi.org/10.1007/978-3-540-89985-3_30
Publisher Name: Springer, Berlin, Heidelberg
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