Performance Enhancement of Asynchronous Circuits

Abstract

This paper proposes a methodology for automatic slack matching of QDI circuits utilized in a framework of asynchronous synthesis toolset. Slack matching is the problem of adding buffers to an asynchronous pipeline design to prevent stalls and improve performance. This technique is based on Simulated Annealing method and exploits the advantages of both static and dynamic performance analysis to provide enough results in an acceptable time. The utilized performance model is a Timed Petri Net (TPN) which can extended to support choice places to capture the conditional behavior of the system. We implemented this method in the framework of asynchronous synthesis tool and optimized circuits using this technique during synthesis process. The results demonstrate that this algorithm is computationally feasible for moderately sized models. Experimental results on a large set of ISCAS benchmarks indicate that our proposed technique can achieve on average 38% enhancement for performance with 26% area penalty.