Abstract
By increasing the complexity of system on a chip (SoC) formal equivalence checking has become more and more important and a major economical issue to detect design faults at early stages of the design cycle in order to reduce time-to-market as much as possible. However, lower level methods such as BDDs and SAT solvers suffer from memory and computational explosion problems to match sizes of industrial designs in formal equivalence verification. In this paper, we describe a hybrid bit- and word-level canonical representation called Linear Taylor Expansion Diagram (LTED) [1] which can be used to check the equivalence between two descriptions in different levels of abstractions. To prove the validity of our approach, it is run on some industrial circuits with application to communication systems and experimental results are compared to those of Taylor Expansion Diagram (TED) which is also a word level canonical representation [2].
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References
Alizadeh, B., Navabi, Z.: Word level symbolic simulation in processor verification. IEE Proceedings Computers and Digital Techniques Journal 151(5), 356–366 (2004)
Ciesielski, M., Kalla, P., Askar, S.: Taylor Expansion Diagrams: A Canonical Representation for verification of data flow designs. IEEE Transactions on computers 55(9), 1188–1201 (2006)
Alizadeh, B., Fujita, M.: A hybrid approach for equivalence checking between system level and RTL descriptions. In: 6th International Workshop on Logic and Synthesis (IWLS), pp. 298–304 (2007)
Koelbl, A., Lu, Y., Mathur, A.: Embedded tutorial: Formal equivalence checking between system-level models and RTL. In: Proceedings of ICCAD, pp. 965–971 (2005)
Vasudevan, S., Viswanath, V., Abraham, J., Tu, J.: Automatic Decomposition for Sequential Equivalence Checking of System Level and RTL Descriptions. In: Proceedings of Formal Methods and Modes for Co-Design (Memocode), pp. 71–80 (2006)
Feng, X., Hu, A.: Early Cutpoint Insertion for High-Level Software vs. RTL Formal Combinational Equivalence Verification. In: Proceedings of the 43th Design Automation Conference (DAC), pp. 1063–1068 (2006)
Kroening, D., Clarke, E., Yorav, K.: Behavioral consistency of C and Verilog programs using bounded model checking. In: Proceedings of the 40th Design Automation Conference (DAC), pp. 368–371 (2003)
Jain, H., Kroening, D., Clarke, E.: Verification of SpecC using Predicate Abstraction. In: Proceedings of Formal Methods and Models for Co-Design (Memocode), pp. 7–16 (2004)
Karfa, C., Mandal, C., Sarkar, D., Pentakota, S.R., Reade, C.: A Formal Verification Method of Scheduling in High-level Synthesis. In: Proceedings of the 7th International Symposium on Quality Electronic Design (ISQED), pp. 71–78 (2006)
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Alizadeh, B., Fujita, M. (2008). Sequential Equivalence Checking Using a Hybrid Boolean-Word Level Decision Diagram. In: Sarbazi-Azad, H., Parhami, B., Miremadi, SG., Hessabi, S. (eds) Advances in Computer Science and Engineering. CSICC 2008. Communications in Computer and Information Science, vol 6. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-89985-3_85
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DOI: https://doi.org/10.1007/978-3-540-89985-3_85
Publisher Name: Springer, Berlin, Heidelberg
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