Abstract
Ternary Content-Addressable Memories are becoming very popular for designing high-throughput address lookup engines on routers: they are fast, cost-effective and simple to manage. Despite the TCAMs speed, their high power consumption is their major drawback.In this document, we designed a heuristic to match entries in TCAM stages so that only a bounded number of entries are looked up during the search operation.
The performance evaluation of the proposed approach shows that it can save considerable amount of routing table’s power consumption.
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Mahini, A., Berangi, R., Mohtashami, H., Mahini, H. (2008). Low Power and Storage Efficient Parallel Lookup Engine Architecture for IP Packets. In: Sarbazi-Azad, H., Parhami, B., Miremadi, SG., Hessabi, S. (eds) Advances in Computer Science and Engineering. CSICC 2008. Communications in Computer and Information Science, vol 6. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-89985-3_88
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DOI: https://doi.org/10.1007/978-3-540-89985-3_88
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