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Power-Aware Real-Time Scheduling upon Dual CPU Type Multiprocessor Platforms

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Principles of Distributed Systems (OPODIS 2008)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 5401))

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Abstract

Nowadays, most of the energy-aware real-time scheduling algorithms belong to the DVFS (Dynamic Voltage and Frequency Scaling) framework. These DVFS algorithms are usually efficient but, in addition to often consider unrealistic assumptions: they do not take into account the current evolution of the processor energy consumption profiles. In this paper, we propose an alternative to the DVFS framework which preserves energy, while considering the emerging technologies. We introduce a dual CPU type multiprocessor platform model (compatible with any general-purpose processor) and a non-DVFS associated methodology which considerably simplifies the energy-aware real-time scheduling problem, while providing significant energy savings.

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References

  1. Baruah, S., Anderson, J.: Energy-aware implementation of hard-real-time systems upon multiprocessor platform. In: Proceedings of the 16th International Conference on Parallel and Distributed Computing Systems, pp. 430–435 (August 2003)

    Google Scholar 

  2. Jerraya, A., Wolf, W.: Multiprocessor Systems-on-Chips. Morgan Kaufmann, Elsevier (2005)

    Google Scholar 

  3. Veeravalli, B., Goh, L., Viswanathan, S.: Design of fast and efficient energy-aware gradient-based scheduling algorithms heterogeneous embedded multiprocessor systems. IEEE Transactions on Parallel and Distributed Systems 99(1) (2008)

    Google Scholar 

  4. Gorjiara, B., Bagherzadeh, N., Chou, P.: An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes. In: Proceedings of 2004 International Symposium on Low Power Electronics and Design, pp. 381–386 (2004)

    Google Scholar 

  5. Gorjiara, B., Bagherzadeh, N., Chou, P.: Ultra-fast and efficient algorithm for energy optimization by gradient-based stochastic voltage and task scheduling. ACM Transactions on Design Automation of Electronic Systems 12(4) (September 2007)

    Google Scholar 

  6. Gorjiara, B., Chou, P., Bagherzadeh, N., Reshadi, M., Jensen, D.: Fast and efficient voltage scheduling by evolutionary slack distribution. In: Proceedings of Asia and South Pacific Design Automation Conference, pp. 659–662 (January 2004)

    Google Scholar 

  7. Gruian, F., Kuchcinski, K.: Lenes: Task scheduling for low-energy systems using variable supply voltage processors. In: Proceedings of Asia and South Pacific Design Automation Conference, pp. 449–455 (January 2001)

    Google Scholar 

  8. Liu, Y., Veeravalli, B., Viswanathan, S.: Novel critical-path based low-energy scheduling algorithms for heterogeneous multiprocessor real-time embedded systems. In: 13th International Conference on Parallel and Distributed Systems, pp. 1–8 (2007)

    Google Scholar 

  9. Luo, J., Jha, N.K.: Power-conscious joint scheduling of periodic task graphs and aperiodic tasks in distributed real-time embedded systems. In: Proceedings of International Conference on Computer-Aided Design, pp. 357–364 (November 2000)

    Google Scholar 

  10. Rae, A., Parameswaran, S.: Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation. In: Proceedings of Design Automation Conference, pp. 147–152 (2000)

    Google Scholar 

  11. Yu, Y., Prasanna, V.K.: Resource allocation for independent real-time tasks in heterogeneous systems for energy minimization. Journal of Information Science and Engineering 19(3) (May 2003)

    Google Scholar 

  12. Andrei, A., Schmitz, M.T., Eles, P., Peng, Z., Al-Hashimi, B.M.: Overhead-conscious voltage selection for dynamic and leakage energy reduction of time-constrained systems. In: IEEE Proceedings - Computers and Digital Techniques, pp. 28–38 (2005)

    Google Scholar 

  13. Zhang, Y., Hu, X., Chen, D.Z.: Task scheduling and voltage selection for energy minimization. In: Proceedings of 39th Design Automation Conference, pp. 183–188 (June 2002)

    Google Scholar 

  14. Schmitz, M.T., Al-Hashimi, B.: Considering power variations of DVS processing elements for energy minimisation in distributed systems. In: Proceedings of International Symposium on Systems Synthesis, pp. 250–255 (October 2001)

    Google Scholar 

  15. Leung, L.F., Tsui, C.Y., Ki, W.H.: Minimizing energy consumption of multiple-processors-core systems with simultaneous task allocation, scheduling and voltage assignment. In: Proceedings of Asia and South Pacific Design Automation Conference, pp. 647–652 (2004)

    Google Scholar 

  16. Schmitz, M., Al-Hashimi, B., Eles, P.: Energy-efficient mapping and scheduling for DVS enabled distributed embedded systems. In: Proceedings of Design, Automation and Test in Europe Conference and Exhibition, pp. 514–521 (2002)

    Google Scholar 

  17. Oyama, Y., Ishihara, T., Sato, T., Yasuura, H.: A multi-performance processor for low power embedded applications. In: Proc. of COOL Chips X IEEE Symposium on Low-Power and High-Speed Chips, p. 138 (2007)

    Google Scholar 

  18. Ekekwe, N., Etienne-Cummings, R.: Power dissipation sources and possible control techniques in ultra deep submicron cmos technologies. Microelectronics Journal 37(9), 851–860 (2006)

    Article  Google Scholar 

  19. Taur, Y., Nowark, E.: CMOS devices below 0.1 um: how high will performance go? In: Electron Devices Meeting, Technical Digest, pp. 215–218. International Publication (1997)

    Google Scholar 

  20. Mukhopadhyay, S., Roy, K., Mahmoodi-Meimand, H.: Leakage current mechanisms and leakage reduction techniques in deep-submicron CMOS circuits. Proceedings of the IEEE 91(2), 305–327 (2003)

    Article  Google Scholar 

  21. Leroy, A.: Optimizing the on-chip communication architecture of low power Systems-on-Chip in Deep Sub-Micron technology. PhD thesis, Université Libre de Bruxelles (2006)

    Google Scholar 

  22. Annavaram, M., Grochowski, E., Shen, J.: Mitigating Amdahl’s law through EPI throttling. In: Proceedings of the 32nd Annual International Symposium on Computer Architecture, pp. 298–309 (2005)

    Google Scholar 

  23. Kumar, R., Farkas, K.I., Jouppi, N.P., Ranganathan, P., Tullsen, D.M.: Single-ISA heterogeneous multi-core architectures: The potential for processor power reduction. In: Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 81–92 (2003)

    Google Scholar 

  24. Kumar, R., Tullsen, D.M., Ranganathan, P., Jouppi, N.P., Farkas, K.I.: Single-ISA heterogeneous multi-core architectures for multithreaded workload performance. In: Proceedings of the 31st Annual International Symposium on Computer Architecture, pp. 64–75 (2004)

    Google Scholar 

  25. Benini, L., Micheli, G.D.: Networks on Chips: A New SoC Paradigm. Computer 35(1), 70–78 (2002)

    Article  Google Scholar 

  26. Towles, B., Dally, W.J.: Route packets, not wires: On-chip interconnection networks. Design Automation Conference 0, 684–689 (2001)

    Google Scholar 

  27. Wolkotte, P.T., Smit, G.J.M., Kavaldjiev, N., Becker, J.E., Becker, J.: Energy model of networks-on-chip and a bus. In: 2005 International Symposium on System-on-Chip, 2005. Proceedings, pp. 82–85 (2005)

    Google Scholar 

  28. Bolotin, E., Cidon, I., Ginosar, R., Kolodny, A.: Cost considerations in network on chip. Integr. VLSI J. 38(1), 19–42 (2004)

    Article  Google Scholar 

  29. Baruah, S., Mok, A., Rosier, L.: Preemptively scheduling hard-real-time sporadic tasks on one processor. In: Proceedings of the 11th real-time systems symposium, Orlando, Florida, pp. 182–190 (1990)

    Google Scholar 

  30. Baruah, S., Baker, T.: Schedulability analysis of global EDF. Real-Time Systems 38(3), 223–235 (2008)

    Article  MATH  Google Scholar 

  31. Ripoll, I., Crespo, A., Mok, A.K.: Improvement in feasibility testing for real-time tasks. Real-Time Systems 11(1), 19–39 (1996)

    Article  Google Scholar 

  32. Baker, T., Fisher, N., Baruah, S.: Algorithms for determining the load of a sporadic task system. Technical Report TR-051201, Department of Computer Science, Florida State University (2005)

    Google Scholar 

  33. Fisher, N., Baker, T., Baruah, S.: Algorithms for determining the demand-based load of a sporadic task system. In: Proceedings of the 12th International Conference on Embedded and Real-Time Computing, pp. 135–146 (2006)

    Google Scholar 

  34. Fisher, N., Baruah, S., Baker, T.P.: The partitioned scheduling of sporadic tasks according to static-priorities. In: Euromicro Conference on Real-Time Systems, vol. 0, pp. 118–127 (2006)

    Google Scholar 

  35. Baker, T.: Multiprocessor EDF and deadline monotonic schedulability analysis. In: Proceedings of the 24th IEEE International Real-Time Systems Symposium, pp. 120–129 (2003)

    Google Scholar 

  36. Baruah, S., Cohen, N., Plaxton, C., Varvel, D.: Proportionate progress: A notion of fairness in resource allocation. Algorithmica 15(6), 600–625 (1996)

    Article  MathSciNet  MATH  Google Scholar 

  37. Dertouzos, M., Mok, A.: Multiprocessor on-line scheduling of hard-real-time tasks. IEEE Transactions on Software Engineering 15(2), 1497–1506 (1989)

    Article  Google Scholar 

  38. Cho, H., Ravindran, B., Jensen, E.D.: An Optimal Real-Time Scheduling Algorithm for Multiprocessors. In: Proceedings of the 27th IEEE International Real-Time Systems Symposium, pp. 101–110 (2006)

    Google Scholar 

  39. Real, J., Crespo, A.: Mode change protocols for real-time systems: A survey and a new proposal. Real-Time Systems 26(2), 161–197 (2004)

    Article  MATH  Google Scholar 

  40. Nélis, V., Goossens, J.: Mode change protocol for multi-mode real-time systems upon identical multiprocessors. Technical Report arXiv:0809.5238v1, Cornell University (September 2008)

    Google Scholar 

  41. Bertogna, M., Cirinei, M., Lipari, G.: Improved schedulability analysis of EDF on multiprocessor platforms. In: Proceedings of the 17th Euromicro Conference on Real-Time Systems, pp. 209–218 (2005)

    Google Scholar 

  42. Goldberg, D.E.: Genetic Algorithms in Search, Optimization, and Machine Learning, vol. 1. Addison-Wesley Professional, Reading (1989)

    MATH  Google Scholar 

  43. Kirkpatrick, S., Gelatt, C.D., Vecchi, M.P.: Optimization by simulated annealing. Science 220(4598), 671–680 (1983)

    Article  MathSciNet  MATH  Google Scholar 

  44. D&R Industry Articles: Diamond standard processor core family architecture. Tensilica White Paper (July 2007)

    Google Scholar 

  45. Halfhill, T.R.: Tensilica’s preconfigured cores: Six embedded-processor cores challenge ARM, ARC, MIPS, and DSPs. Microprocessor Report (2006)

    Google Scholar 

  46. Gavrichenkov, I.: Meet intel wolfdale: Core 2 duo e8500, e8400 and e8200 processors review (2008)

    Google Scholar 

  47. Aydin, R., Melhem, R., Mossé, D., Mejia-Alvarez, P.: Power-aware scheduling for periodic real-time tasks. IEEE Transactions on Computers 53(5), 584–600 (2004)

    Article  Google Scholar 

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Author information

Authors and Affiliations

  1. Université Libre de Bruxelles, Brussels, Belgium

    Joël Goossens, Dragomir Milojevic & Vincent Nélis

Authors
  1. Joël Goossens
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  2. Dragomir Milojevic
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  3. Vincent Nélis
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Editor information

Editors and Affiliations

  1. Department of Computer Science, Florida State University, 207A Love Building, PO Box 4530, FL 32306-4530, Tallahassee, USA

    Theodore P. Baker

  2. Université de Versailles-St-Quentin-en-Yvelines, 45, avenue des Etats-Unis, 78035, Versailles Cedex, France

    Alain Bui

  3. LIP6 & INRIA Grand Large, Université Pierre et Marie Curie - Paris 6, 104 avenue du Président Kennedy, 75016, Paris, France

    Sébastien Tixeuil

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Goossens, J., Milojevic, D., Nélis, V. (2008). Power-Aware Real-Time Scheduling upon Dual CPU Type Multiprocessor Platforms. In: Baker, T.P., Bui, A., Tixeuil, S. (eds) Principles of Distributed Systems. OPODIS 2008. Lecture Notes in Computer Science, vol 5401. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-92221-6_25

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  • DOI: https://doi.org/10.1007/978-3-540-92221-6_25

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-92220-9

  • Online ISBN: 978-3-540-92221-6

  • eBook Packages: Computer ScienceComputer Science (R0)

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