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Software Pipelining in Nested Loops with Prolog-Epilog Merging

  • Conference paper
High Performance Embedded Architectures and Compilers (HiPEAC 2009)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 5409))

Abstract

Software pipelining (or modulo scheduling) is a powerful back-end optimization to exploit instruction and vector parallelism. Software pipelining is particularly popular for embedded devices as it improves the computation throughput without increasing the size of the inner loop kernel (unlike loop unrolling), a desirable property to minimize the amount of code in local memories or caches. Unfortunately, common media and signal processing codes exhibit series of low-trip-count inner loops. In this situation, software pipelining is often not an option: it incurs severe fill/drain time overheads and code size expansion due to nested prologs and epilogs.

We propose a method to pipeline series of inner loops without increasing the size of the loop nest, apart from an outermost prolog and epilog. Our method achieves significant code size savings and allows pipelining of low-trip-count loops. These benefits come at the cost of additional scheduling constraints, leading to a linear optimization problem to trade memory usage for pipelining opportunities.

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Authors and Affiliations

  1. Alchemy Group, INRIA Saclay, France, and HiPEAC Network, France

    Mohammed Fellahi & Albert Cohen

Authors
  1. Mohammed Fellahi
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  2. Albert Cohen
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Editor information

Editors and Affiliations

  1. IRISA, Campus de Beaulieu, 35042, Rennes Cedex, France

    André Seznec

  2. Intel Corporation, Massachusetts Microprocessor Design Center, 77 Reed Road, MA 01749, Hudson, USA

    Joel Emer

  3. School of Informatics, Institute for Computing Systems Architecture, King’ s Buildings, EH9 3JZ, Edinburgh, United Kingdom

    Michael O’Boyle

  4. Department of Electrical Engineering, Princeton University, 34 Olden Street, NJ 08544-5263, Princeton, USA

    Margaret Martonosi

  5. Department of Computer Science, University of Augsburg, 86135, Augsburg, Germany

    Theo Ungerer

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© 2009 Springer-Verlag Berlin Heidelberg

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Fellahi, M., Cohen, A. (2009). Software Pipelining in Nested Loops with Prolog-Epilog Merging. In: Seznec, A., Emer, J., O’Boyle, M., Martonosi, M., Ungerer, T. (eds) High Performance Embedded Architectures and Compilers. HiPEAC 2009. Lecture Notes in Computer Science, vol 5409. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-92990-1_8

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  • DOI: https://doi.org/10.1007/978-3-540-92990-1_8

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-92989-5

  • Online ISBN: 978-3-540-92990-1

  • eBook Packages: Computer ScienceComputer Science (R0)

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