Abstract
As the device size continues to shrink and circuit complexity continues to grow, power has become the limiting factor in today’s microprocessor design. Since the power dissipation is a function of many variables with uncertainty, the most accurate representation of chip power or macro power is a statistical distribution subject to process and workload variation, instead of a single number for the average or worst-case power. Unlike statistical timing models that can be represented as a linear canonical form of Gaussian distributions, the exponential dependency of leakage power on process variables, as well as the complex relationship between switching power and workload fluctuations, present unique challenges in statistical power analysis. This paper presents a comprehensive case study on the statistical distribution of dynamic switching power and static leakage power to demonstrate the characterization and correlation methods for macro-level and chip-level power analysis.
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Chen, H., Neely, S., Xiong, J., Zolotov, V., Visweswariah, C. (2009). Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power. In: Svensson, L., Monteiro, J. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-95948-9_18
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DOI: https://doi.org/10.1007/978-3-540-95948-9_18
Publisher Name: Springer, Berlin, Heidelberg
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