Abstract
Virtual channels are a common alternative for providing quality-of-service to Networks-on-Chip. A drawback of the approach is the increased power consumption because of the suppression of correlation between consecutive flits. This work proposes an architecture based on low-power coding to overcome the aforementioned problem. The technique requires a minimum overhead, while obtaining a significant power reduction (45% in the average case). Exhaustive experimental simulations are provided to demonstrate the advantages of the proposed architecture.
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García-Ortiz, A., Indrusiak, L.S., Murgan, T., Glesner, M. (2009). PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels. In: Svensson, L., Monteiro, J. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-95948-9_22
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DOI: https://doi.org/10.1007/978-3-540-95948-9_22
Publisher Name: Springer, Berlin, Heidelberg
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