Abstract
Power distribution systems provide the voltages and currents that devices in a circuit need to operate properly and silicon success requires its careful design and verification. However, problems like voltage drop, ground bounce and electromigration, which may cause chip failures, are worsening, as more devices, operating at higher frequencies, are placed closer together. Verification of this type of systems is usually done by simulation, a costly endeavor given the size of current grids, making the determination of the worst-case input setting a crucial task. Current methodologies are based on supposedly safe settings targeting either unrealistic simultaneous switching on all signals or heuristic accounts of the joint switching probability of nearby signals. In this paper we propose a methodology for computation of the worst-case stimuli for power grid analysis. This is accomplished by determining the input vector that maximizes the number of gates, in close proximity to each other, that can switch in a given time window. The addition of these temporal and spatial restrictions makes the solution of the underlying optimization problem feasible. Comparisons with existing alternatives show that only a fraction of the gates change in any given timing window, leading to a more robust and efficient verification methodology.
This research was supported in part by the Portuguese FCT under program POSI, ref. EEA-ESE/61528/2004.
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Morgado, P.M., Flores, P.F., Monteiro, J.C., Silveira, L.M. (2009). Generating Worst-Case Stimuli for Accurate Power Grid Analysis. In: Svensson, L., Monteiro, J. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-95948-9_25
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DOI: https://doi.org/10.1007/978-3-540-95948-9_25
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