Abstract
In this paper we demonstrate and analyse how the differential ultra low voltage inverter can be designed in order to achieve the most beneficial conditions concerning speed, stability and EDP.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Verma, N., Kwong, J., Chandrakasan, A.: Nanometer mosfet variation in minimum energy subthreshold circuits. IEEE Transactions on Electron Devices 55(1), 847–854 (1995)
Chandrakasan, A.P., Sheng, S., Brodersen, R.W.: Low-power CMOS digital design. IEEE Journal of Solid-State Circuits 27(4), 473–484 (1992)
Burr, J.B., Peterson, A.M.: Ultra low power CMOS technology. In: NASA VLSI Design Symposium, pp. 4.2.1 – 4.2.13 (1991)
Burr, J.B., Shott, J.: A 200mV self-testing encoder/decoder using stanford ultra low-power CMOS. In: International Solid-State Circuits Conference (ISSCC), pp. 84–85. IEEE, Los Alamitos (1994)
Usami, K., Horowitz, M.: Clustered voltage scaling technique for low-power design. In: International Symposium on Low Power Electronics and Design, pp. 3–8. IEEE, Los Alamitos (1995)
Berg, Y., Wisland, D.T., Lande, T.S.: Ultra low-voltage/low-power digital floating-gate circuits. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 46(7), 930–936 (1999)
Berg, Y., Mirmotahari, O., Norseng, P.A., Aunet, S.: Ultra low voltage CMOS gate. In: International Conference on Electronics, Circuits and Systems (ICECS), pp. 818–821. IEEE, Los Alamitos (2006)
Mirmotahari, O., Berg, Y.: Digital ultra low voltage high speed logic. In: PATMOS, pp. 1–1. IEEE, Los Alamitos (submitted, 2008)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2009 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Mirmotahari, O., Berg, Y. (2009). Ultra Low Voltage High Speed Differential CMOS Inverter. In: Svensson, L., Monteiro, J. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-95948-9_33
Download citation
DOI: https://doi.org/10.1007/978-3-540-95948-9_33
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-95947-2
Online ISBN: 978-3-540-95948-9
eBook Packages: Computer ScienceComputer Science (R0)