Abstract
Micro-architectural power macro-models dictate the power budget of a new chip design. Based on the early feasibility studies, power specification of new features are defined and then verified all through the design cycle. In this paper, we introduce a novel power-aware design paradigm that aligns power macro-models by mapping power-significant events at all levels of design hierarchy. We apply this paradigm on a state-of-the-art 65nm high-performance micro-processor and demonstrate significant benefits in power optimization at RTL implementation.Moreover, this approach facilitates a feedback loop from the design implementation to higher level (micro-architectural) power models and thus has built-in potential for more accurate power models.
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References
Brooks, D., Bose, P., Srinivasan, V., Gshwind, M.K., Emma, P.G., Rosenfield, M.G.: New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessor. IBM J. RES. & DEV. 47 (2003)
Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A Framework for Micro-architectural Power Analysis and Optimization. In: Proc. of Intl. Symposium on Computer Architecture (2000)
Cai, G., Lim, C.H.: Architectural Level Power/Performance Optimization and Dynamic Power Estimation. Cool Chips Tutorial in conjunction with MICRO 32 ( November 1999)
Calder, B.: Simpoint website (2003), http://www.cse.ucsd.edu/calder/simpoint/
Chen, Z., Roy, K., Chong, E.: Estimation of Power Sensitivity in Sequential Circuits with Power Macro Modeling Application. In: Proc. ICCAD (1998)
Chen, Z., Roy, K.: A power macromodeling technique based on power sensitivity. In: DAC 1998 (1998)
Devadas, S., Malik, S.: A Survey of Optimization Techniques Targeting Low Power VLSI Circuits. In: Proceedings of DAC 1995 (1995)
Kim, T., Chung, K., Liu, C.: A Static Estimation Technique of Power Sensitivity in Logic Circuits. In: Proc. DAC (2001)
Marculescu, D., Marculescu, R., Pedram, M.: Information Theoretic Measure of Energy Consumption at Register Transfer Level. In: ACM/IEEE Intl. Symposium on Low Power Design (1995)
Nemani, M., Najm, F.: Towards a High-Level Power Estimation Capability. IEEE Trans. on CAD (1996)
SungKim, N., Austin, T., Mudge, T., Grunwald, D.: Challenges for architectural level power modeling. Kluwer Academic Publishers, Dordrecht (2002)
Viswanath, V., Abraham, J., Hunt Jr., W.A.: Automatic Insertion of Low Power Annotations in RTL for Pipelined Microprocessor. In: Design Automation and Test in Europe DATE, Munich (2006)
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Aizik, Y., Kamhi, G., Zbar, Y., Ronen, H., Abozaed, M. (2009). Power-Aware Design via Micro-architectural Link to Implementation. In: Svensson, L., Monteiro, J. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-95948-9_8
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DOI: https://doi.org/10.1007/978-3-540-95948-9_8
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-95947-2
Online ISBN: 978-3-540-95948-9
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