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A New Datapath Merging Method for Reconfigurable System

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Reconfigurable Computing: Architectures, Tools and Applications (ARC 2009)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 5453))

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Abstract

Reconfigurable systems have been proved to achieve significant performance speed-up by mapping the most time-consuming loops to a reconfigurable units. Datapath merging (DPM) synthesis has identified the similarities among the Data Flow Graphs (DFGs) corresponding to the loops, and produces a single reconfigurable datapath that can be dynamically reconfigured to execute each DFG. This paper presents a new datapath merging method that produces a reconfigurable datapath with minimal area usage. At first it merges DFGs together one by one to create the reconfigurable datapath. Then it merges the functional units and interconnection units inside the reconfigurable datapath to reduce resource area usage. To do this, a new graph-based technique to merge the resources in the reconfigurable datapath is presented. We evaluate the proposed method using programs from the Media-bench benchmarks and experimental results show a decrease from 5% to 15% in reconfigurable data path resource area in comparison to previous algorithms.

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References

  1. Compton, K., Hauck, S.: Automatic Design of Area-Efficient Configurable ASIC Cores. IEEE Transaction on Computers (TC) 56(5), 1–11 (2007)

    Article  MathSciNet  Google Scholar 

  2. Gajski, D., Dutt, N., Wu, A., Lin, S.: High-Level Synthesis-Introduction to Chip and System Design. Kluwer, Boston (1992)

    Google Scholar 

  3. De Micheli, G.: Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York (1994)

    Google Scholar 

  4. Moreano, N., Borin, E., de Souza, C., Araujo, G.: Efficient Datapath Merging for Partially Reconfigurable architectures. IEEE Transaction on Computer Aided Design 24(7), 969–980 (2005)

    Article  Google Scholar 

  5. Papadimitriou, C., Steiglitz, K.: Combinatorial Optimization-Algorithms and Complexity. Dover, New York (1998)

    MATH  Google Scholar 

  6. Mathur, A., Sanjive, S.: Improved Merging of Datapath Operators Using Information Content and Required Precision Analysis. In: Proceeding of Design Automation Conference (DAC), Rhode Island, pp. 462–467 (April 2001)

    Google Scholar 

  7. Memik, S.O., Memik, G., Jafari, R., Kursun, E.: Global resource sharing for synthesis of control data flow graphs on FPGAs. In: Proceedings of the 40th Conference on Design Automation (DAC), Anaheim, CA, USA, pp. 2–6 (June 2003)

    Google Scholar 

  8. Brisk, P., Kaplan, A., Sarrafzadeh, M.: Area-efficient instruction set synthesis for reconfigurable system-on-chip designs. In: Proceedings of the 41st Annual Conference on Design Automation (DAC), San Diego, CA, USA, pp. 395–400 (June 2004)

    Google Scholar 

  9. Chavet, C., Andriamisaina, C., Coussy, Ph., Casseau, E., Juin, E., Urard, P., Martin, E.: A design flow dedicated to Multimode Architectures for DSP Applications. In: Proceeding of (ICCAD), San Jose, CA, USA, pp. 604–611 (November 2007)

    Google Scholar 

  10. Moreano, N., Araujo, G., Huang, Zh., Majlik, S.H.: Datapath Merging and Interconnection Sharing for Reconfigurable Architectures. In: Proceeding of International Symposium on Systems Synthesis (ISSS), Kyoto, Japan, pp. 38–43 (January 2002)

    Google Scholar 

  11. de Souza, C., Lima, A.M., Moreano, N., Araujo, G.: The Datapath Merging Problem in Reconfigurable Systems: Lower Bounds and Heuristic Evaluation. ACM Journal of Experimental Algorithmics (JEA) 10(2), 1–19 (2006)

    MATH  Google Scholar 

  12. Garey, M., Johnson, D.S.: Computers and Intractability-A Guide to the Theory of NP-Completeness. Freeman, San Francisco (1979)

    MATH  Google Scholar 

  13. Ostergard, P.R.J.: A New Algorithm for the Maximum-Weight Clique Problem. Nordic Journal of Computing (NJC) 8(4), 424–436 (2002)

    MathSciNet  Google Scholar 

  14. Lee, C., Potkonjak, M., Mangione, W.S.: Media-bench: a tool for evaluating and synthesizing multimedia and communication systems. In: Proceedings of The thirtieth Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-03), California, USA, pp. 330–335 (December 1997)

    Google Scholar 

  15. GNU Compiler Collection Internals, http://gcc.gnu.org/onlinedocs

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© 2009 Springer-Verlag Berlin Heidelberg

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Fazlali, M., Fallah, M.K., Zolghadr, M., Zakerolhosseini, A. (2009). A New Datapath Merging Method for Reconfigurable System. In: Becker, J., Woods, R., Athanas, P., Morgan, F. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2009. Lecture Notes in Computer Science, vol 5453. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-00641-8_17

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  • DOI: https://doi.org/10.1007/978-3-642-00641-8_17

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-00640-1

  • Online ISBN: 978-3-642-00641-8

  • eBook Packages: Computer ScienceComputer Science (R0)

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