Abstract
There are many examples in the literature of applications that show different communication needs within a MPSoC. Very often cores interconnected through a Network-on-Chip have routers containing different buffers size, with different clock speed requirements. In this context, we are proposing a dynamic reconfigurable router for a NoC. With the proposed architecture it is possible to reconfigure the depth of each FIFO of the channel inside the routers. It allows more reusability in the NoC since the FIFO depth in the channels can be defined in accordance with the application. Besides, a buffer that is not used by its own channel can be used by others channel, reducing the power consumption.
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Matos, D., Concatto, C., Carro, L., Kastensmidt, F., Susin, A. (2009). The Need for Reconfigurable Routers in Networks-on-Chip. In: Becker, J., Woods, R., Athanas, P., Morgan, F. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2009. Lecture Notes in Computer Science, vol 5453. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-00641-8_28
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DOI: https://doi.org/10.1007/978-3-642-00641-8_28
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-00640-1
Online ISBN: 978-3-642-00641-8
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