Abstract
Spiking Neural Networks (SNNs) model the biological functions of the human brain enabling neuro/computer scientists to investigate how arrays of neurons can be used to solve computational tasks. However, as network models approach the biological scale with significantly large numbers of neurons, existing software simulation environments face the problem of scalability and increasing simulation times. Emulation in hardware offers a significant increase in the acceleration of simulations through the exploitation of parallelism and dedicated on-chip training. However, it is important that the configuration of SNNs for hardware emulation is abstracted from the novice end-user to allow flexible, high-level specification and execution. This paper presents a novel reconfigurable hardware architecture and internet-based configuration environment for the FPGA-based acceleration of SNNs with online training. Results are presented to demonstrate the acceleration performance.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Maass, W.: Computation with Spiking Neurons: The Handbook of Brain Theory and Neural Networks. MIT Press, Cambridge (2001)
Hines, M.L., et al.: The NEURON Simulation Environment. In: The Handbook of Brain Theory and Neural Networks, 2nd edn., pp. 769–773. MIT Press, Cambridge (2003)
Furber, S., et al.: SpiNNaker: Mapping NNs onto a Massively-Parallel Chip Multiprocessor. In: IEEE World Congress on Computational Intelligence (2008)
Maguire, L.P., et al.: Challenges for Large-scale Implementations of SNNs on FPGAs. Neurocomputing 71(1-3), 13–29 (2007)
Vogelstein, R., et al.: Dynamically Reconfigurable Silicon Array of Spiking Neurons with Conductance-Based Synapses. IEEE Trans. Neural Nets 18(1), 253–265 (2007)
Harkin, J., et al.: Reconfigurable Platforms & the Challenges for Large-Scale Implementations of SNNs. In: IEEE Field Prog. Logic & Apps (FPL) Conf., pp. 483–486 (2008)
Rocke, P., et al.: Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controller. Applied Reconfigurable Computing, 373–378 (2007)
Merolla, P., Boahen, K.: Expandable Networks for Neuromorphic Chips. IEEE Trans Circuits and Systems I 54(2), 301–311 (2007)
Glackin, B., et al.: Novel Approach for the Implementation of Large-Scale SNNs on FPGAs. In: Artificial NNs Conference (2005)
Upegui, A., et al.: An FPGA platform for on-line topology exploration of SNNs. Microprocessors & Microsystems 29(5) (2005)
Pearson, M.P., et al.: Implementing SNNs for Real-Time Signal-Processing and Control Applications: A Model-Validated FPGA Approach. IEEE Trans. Neural Nets 18(5) (2007)
Torres-Huitzil, C., et al.: Hardware/Software Co-design for Embedded Implementation of Neural Networks. In: Applied Reconfigurable Computing Workshop, pp. 167–178 (2007)
Wu, Q.X., et al.: Adaptive Co-Ordinate Transformation Based on Spike Timing-Dependent Plasticity Learning Paradigm. In: Wang, L., Chen, K., S. Ong, Y. (eds.) ICNC 2005. LNCS, vol. 3610, pp. 420–428. Springer, Heidelberg (2005)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2009 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Glackin, B., Harkin, J., McGinnity, T.M., Maguire, L.P. (2009). A Hardware Accelerated Simulation Environment for Spiking Neural Networks. In: Becker, J., Woods, R., Athanas, P., Morgan, F. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2009. Lecture Notes in Computer Science, vol 5453. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-00641-8_38
Download citation
DOI: https://doi.org/10.1007/978-3-642-00641-8_38
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-00640-1
Online ISBN: 978-3-642-00641-8
eBook Packages: Computer ScienceComputer Science (R0)