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A HyperTransport 3 Physical Layer Interface for FPGAs

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Reconfigurable Computing: Architectures, Tools and Applications (ARC 2009)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 5453))

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Abstract

This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high bandwidth point-to-point interconnect technology that can be used to directly connect hardware accelerators to AMD’s Opteron CPUs. Providing support for HyperTransport 3 on FPGAs is highly relevant for increasing the performance of accelerators based on reconfigurable logic. This paper shows the challenges of such an implementation and novel ideas to solve them successfully. A new architecture is presented that uses Fast Serializer Logic to keep up with the increasing speeds of current host interface protocols. A solid evaluation is provided using a specially developed FPGA board as a verification platform.

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© 2009 Springer-Verlag Berlin Heidelberg

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Litz, H., Froening, H., Bruening, U. (2009). A HyperTransport 3 Physical Layer Interface for FPGAs. In: Becker, J., Woods, R., Athanas, P., Morgan, F. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2009. Lecture Notes in Computer Science, vol 5453. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-00641-8_4

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  • DOI: https://doi.org/10.1007/978-3-642-00641-8_4

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-00640-1

  • Online ISBN: 978-3-642-00641-8

  • eBook Packages: Computer ScienceComputer Science (R0)

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