Abstract
We present a systematic approach to design and verification of fault-tolerant components with real-time properties as found in embedded systems. A state machine model of the correct component is augmented with internal transitions that represent hypothesized faults. Also, constraints on the occurrence or timing of faults are included in this model. This model of a faulty component is then extended with fault detection and recovery mechanisms, again in the form of state machines. Desired properties of the component are model checked for each of the successive models. The models can be made relatively detailed such that they can serve directly as blueprints for engineering, and yet be amenable to exhaustive verification. The approach is illustrated with a design of a triple modular fault-tolerant system that is a real case we received from our collaborators in the aerospace field. We use UPPAAL to model and check this design. Model checking uses concrete parameters, so we extend the result with parametric analysis using abstractions of the automata in a rigorous verification.
Research supported by project No. 60603037, the National Natural Science Foundation of China and the HTTS project funded by Macau Science and Technology Development Foundation.
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References
Abadi, M., Lamport, L.: The existence of refinement mapping. Theoretical Computer Science 82(2), 253–284 (1991)
Alur, R., Dill, D.L.: A Theory of Timed Automata. Theoretical Computer Science 126(2), 183–235 (1994)
Avizienis, A., Laprie, J.-C., Randell, B.: Fundamental Concepts of Dependability. In: Proceedings of the 3rd IEEE Information Survivability Workshop (ISW 2000), pp. 7–12 (2000)
Behrmann, G., David, A., Larsen, K.G.: A tutorial on uppaal. In: Bernardo, M., Corradini, F. (eds.) SFM-RT 2004. LNCS, vol. 3185, pp. 200–236. Springer, Heidelberg (2004)
Bernardeschi, C., Fantechi, A., Gnesi, S.: Model checking fault tolerant systems. Journal of Software Testing, Verification and Reliability (STVR) 12(4), 251–275 (2002)
Clarke, E.M., Grumberg, O., Long, D.E.: Model Checking and Abstraction. ACM Transations on Programming Languadge and Ststems 16(5), 1512–1542 (1992)
Cousot, P., Cousot, R.: On abstraction in software verification. In: Brinksma, E., Larsen, K.G. (eds.) CAV 2002. LNCS, vol. 2404, pp. 37–56. Springer, Heidelberg (2002)
Dams, D., Gerth, R., Grumberg, O.: Abstract interpretation of reactive systems. ACM Transactions on Programming Languages and Systems (TOPLAS) 19(2), 253–291 (1997)
Devillers, M.C.A., Griffioen, W.O.D., Romijn, J.M.T., Vaandrager, F.W.: Verification of a Leader Election Protocol - Formal Methods Applied to IEEE 1394. Formal Methods in System Design 16(3), 307–320 (2000)
Gebremichael, B., Vaandrager, F.W., Zhang, M.: Analysis of the Zeroconf Protocol Using UPPAAL. In: Proceedings of the 6th Annual ACM & IEEE Conference on Embedded Software (EMSOFT 2006), pp. 242–251. ACM Press, New York (2006)
Gnesi, S., Lenzini, G., Martinelli, F.: Logical specification and analysis of fault tolerant systems through partial model checking. In: Proceedings of the International Workshop on Software Verification and Validation (SVV 2003). Electronic Notes in Theoretical Computer Science, vol. 118, pp. 57–70 (2003)
Jensen, H.E.: Abstraction-Based Verification of Distributed Systems. Phd thesis, Department of Computer Science, Aalborg University, Denmark (June 1999)
Jensen, H.E., Larsen, K.G., Skou, A.: Scaling up uppaal. In: Joseph, M. (ed.) FTRTFT 2000. LNCS, vol. 1926, pp. 19–30. Springer, Heidelberg (2000)
Johnson, B.W.: Design and analysis of fault-tolerant digital systems. Addison-Wesley Publishing, Reading (1989)
Liu, Z., Joseph, M.: Specification and verification of fault-tolerance timing, and scheduling. ACM Transactions on Programming Languages and Systems 21(1), 46–89 (1999)
Liu, Z., Joseph, M.: Verification of fault-tolerance and real time. In: FTCS 1996, pp. 220–229. IEEE Computer Society Press, Los Alamitos (1996)
Loiseaux, C., Graf, S., Sifakis, J., Bouajjani, A., Bensalem, S.: Property Preserving Abstractions for the Verification of Concurrent Systems. Formal Methods in System Design 6(1), 11–44 (1995)
Schneider, F., Easterbrook, S.M., Callahan, J.R., Holzmann, G.J.: Validating requirements for fault tolerant systems using model checking. In: Proceedings of the 3rd International Conference on Requirements Engineering, pp. 4–13. IEEE Computer Society Press, Los Alamitos (1998)
Simons, D.P.L., Stoelinga, M.: Mechanical verification of the IEEE 1394- a root contention protocol using Uppaal2k. International Journal on Software Tools for Technlogy Transfer, 469–485 (2001)
Stoelinga, M.I.A., Vaandrager, F.W.: Root contention in IEEE 1394. In: Katoen, J.-P. (ed.) AMAST-ARTS 1999, ARTS 1999, and AMAST-WS 1999. LNCS, vol. 1601, pp. 53–74. Springer, Heidelberg (1999)
Yorav, K.: Exploiting syntactic structure for automatic verification. PhD thesis, The Technion, Israel Insitute of Technology (2000)
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Zhang, M., Liu, Z., Morisset, C., Ravn, A.P. (2009). Design and Verification of Fault-Tolerant Components. In: Butler, M., Jones, C., Romanovsky, A., Troubitsyna, E. (eds) Methods, Models and Tools for Fault Tolerance. Lecture Notes in Computer Science, vol 5454. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-00867-2_4
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DOI: https://doi.org/10.1007/978-3-642-00867-2_4
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