Abstract
We present a systematic approach to design and verification of fault-tolerant components with real-time properties as found in embedded systems. A state machine model of the correct component is augmented with internal transitions that represent hypothesized faults. Also, constraints on the occurrence or timing of faults are included in this model. This model of a faulty component is then extended with fault detection and recovery mechanisms, again in the form of state machines. Desired properties of the component are model checked for each of the successive models. The models can be made relatively detailed such that they can serve directly as blueprints for engineering, and yet be amenable to exhaustive verification. The approach is illustrated with a design of a triple modular fault-tolerant system that is a real case we received from our collaborators in the aerospace field. We use UPPAAL to model and check this design. Model checking uses concrete parameters, so we extend the result with parametric analysis using abstractions of the automata in a rigorous verification.
Research supported by project No. 60603037, the National Natural Science Foundation of China and the HTTS project funded by Macau Science and Technology Development Foundation.
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Zhang, M., Liu, Z., Morisset, C., Ravn, A.P. (2009). Design and Verification of Fault-Tolerant Components. In: Butler, M., Jones, C., Romanovsky, A., Troubitsyna, E. (eds) Methods, Models and Tools for Fault Tolerance. Lecture Notes in Computer Science, vol 5454. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-00867-2_4
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DOI: https://doi.org/10.1007/978-3-642-00867-2_4
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