Abstract
The complexity of hardware design methodologies represents a significant difficulty for non hardware focused scientists working on CNN-based applications. An emerging generation of Electronic System Level (ESL) design tools is been developed, which allow software-hardware codesign and partitioning of complex algorithms from High Level Language (HLL) descriptions. These tools, together with High Performance Reconfigurable Computer (HPRC) systems consisting of standard microprocessors coupled with application specific FPGA chips, provide a new approach for rapid emulation and acceleration of CNN-based applications. In this article CoDeveloper, and ESL IDE from Impulse Accelerated Technologies, is analyzed. A sequential CNN architecture, suitable for FPGA implementation, proposed by the authors in a previous paper, is implemented using CoDeveloper tools and the DS1002 HPRC platform from DRC Computers. Results for a typical edge detection algorithm shown that, with a minimum development time, a 10x acceleration, when compared to the software emulation, can be obtained.
This is a preview of subscription content, log in via an institution to check access.
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Rodriguez-Vazquez, A., Linan-Cembrano, G., Carranza, L., Roca-Moreno, E., Carmona-Galan, R., Jimenez-Garrido, F., Dominguez-Castro, R., EMeana, S.: ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs. IEEE Transactions on Circuits and Systems I 51(5), 851–863 (2004)
Nagy, Z., Szolgay, P.: Configurable multilayer CNN-UM emulator on FPGA. IEEE Trans. on Circuits and Systems I 50(6), 774–778 (2003)
Perko, M., Fajfar, I., Tuma, T., Puhan, J.: Low-cost, high-performance CNN simulator implemented in FPGA. In: IEEE Int. Work. on Cellular Neural Networks and Their Applications, CNNA, pp. 277–282 (2000)
Malki, S., Spaanenburg, L.: CNN Image Processing on a Xilinx Virtex-II 6000. In: Proceedings ECCTD 2003 (Krakow), pp. 261–264 (2003)
Martínez, J.J., Garrigós, F.J., Toledo, F.J., Ferrández, J.M.: High Performance Implementation of an FPGA-Based Sequential DT-CNN. In: Mira, J., Álvarez, J.R. (eds.) IWINAC 2007. LNCS, vol. 4528, pp. 1–9. Springer, Heidelberg (2007)
Densmore, D., Passerone, R.: A Platform-Based Taxonomy for ESL Design. IEEE Design & Test of Computers 23(5), 359–374 (2006)
DRC Computers (2008), http://www.drccomputer.com
Impulse Accelerated Technologies Inc.(2003-2009), http://www.impulsec.com
Chua, L.O., Yang, L.: Cellular neural networks: theory. IEEE Trans. Circuits and Systems, CAS-35 (1988)
Martínez, J.J., Toledo, F.J., Fernández, E., Ferrández, J.M.: A retinomorphic architecture based on discrete-time cellular neural networks using reconfigurable computing. Neurocomputing 71(4-6), 766–775 (2008)
Martínez, J.J., Toledo, F.J., Fernández, E., Ferrández, J.M.: Study of the contrast processing in the early visual system using a neuromorphic retinal architecture. Neurocomputing 72(4-6), 928–935 (2009)
SRC Computers, LLC (2009), http://www.srccomp.com/
Silicon Graphics, Inc. (2009), http://www.sgi.com
Cray Inc. (2009), http://www.cray.com/
Xilinx Inc., Virtex-4 User Guide, data sheet(ug070) (2004), http://www.xilinx.com
Court, T.V., Herbordt, M.C.: Families of FPGA-Based Accelerators for Approximate String Matching. ACM Microprocessors & Microsystems 31(2), 135–145 (2007)
Kindratenko, V., Pointer, D.: A case study in porting a production scientific supercomputing application to a reconfigurable computer. In: Proc. IEEE Symposium on Field-Programmable Custom Computing Machines - FCCM 2006, pp. 13–22 (2006)
El-Araby, E., El-Ghazawi, T., Le Moigne, J., Gaj, K.: Wavelet Spectral Dimension Reduction of Hyperspectral Imagery on a Reconfigurable Computer. In: IEEE Int. Conference on Field-Programmable Technology (FPT 2004), Brisbane, Australia (December 2004)
Michalski, A., Gaj, K., El-Ghazawi, T.: An Implementation Comparison of an IDEA Encryption Cryptosystem on Two General-Purpose Reconfigurable Computers. In: Proc. FPL 2003, pp. 204–219 (2003)
Storaasli, O.O.: Scientific Applications on a NASA Reconfigurable Hypercomputer. In: 5th MAPLD Int. Conference, Washington, DC, USA (September 2002)
GCC, The GNU Compiler Collection (2009), http://gcc.gnu.org/
FastCam (2009), http://www.iac.es/proyecto/fastcam/
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2009 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Martínez-Álvarez, J.J., Garrigós-Guerrero, F.J., Toledo-Moreo, F.J., Ferrández-Vicente, J.M. (2009). Using Reconfigurable Supercomputers and C-to-Hardware Synthesis for CNN Emulation. In: Mira, J., Ferrández, J.M., Álvarez, J.R., de la Paz, F., Toledo, F.J. (eds) Bioinspired Applications in Artificial and Natural Computation. IWINAC 2009. Lecture Notes in Computer Science, vol 5602. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-02267-8_27
Download citation
DOI: https://doi.org/10.1007/978-3-642-02267-8_27
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-02266-1
Online ISBN: 978-3-642-02267-8
eBook Packages: Computer ScienceComputer Science (R0)