Abstract
VS (Virtual Supervisor) Diagrams, defined from the FPM (Finite Positions Machines) framework, are used to model, analyze and validate automated manufacturing systems and they are obtained, in a practical way, from the PLC (Programmable Logic Controller) signals. This current paper presents a neural network architecture in order to identify that type of diagrams. It is made up of a supervised Hebb neural network cascade linked to a recurrent Hopfield network.
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Gómez, D., Trujillo, J.A., Baeyens, E., Moya, E.J.: Analysis of Production Systems Using the VS-Diagram. In: International Symposium on Distributed Computing and Artificial Intelligence 2008 (DCAI 2008), pp. 443–451 (2008)
Cárdenas, C.: Product Supervisors Design and ECA rules application on Finite Position Machines to Control Manufacturing Processes. Thesis, Universidad de Valladolid (2006)
Trujillo, J.A.: Finite Position Machine for Logic Control: Pattern Composition in Reconfigurable Manufacturing Systems. Thesis. Universidad de Valladolid (2004)
Demuth, H., Beale, M., Hagan, M.: Neural Network Toolbox 6: User’s Guide. The MathWorks, Inc. (2008)
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© 2009 Springer-Verlag Berlin Heidelberg
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Gómez, D., Moya, E.J., Baeyens, E., Cárdenas, C. (2009). VS-Diagrams Identification and Classification Using Neural Networks. In: Omatu, S., et al. Distributed Computing, Artificial Intelligence, Bioinformatics, Soft Computing, and Ambient Assisted Living. IWANN 2009. Lecture Notes in Computer Science, vol 5518. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-02481-8_34
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DOI: https://doi.org/10.1007/978-3-642-02481-8_34
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-02480-1
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