Abstract
Real-time modelling of large neural systems places critical demands on the processing system’s dynamic model. With spiking neural networks it is convenient to abstract each spike to a point event. In addition to the representational simplification, the event model confers the ability to defer state updates, if the model does not propagate the effects of the current event instantaneously. Using the SpiNNaker dedicated neural chip multiprocessor as an example system, we develop models for neural dynamics and synaptic learning that delay actual updates until the next input event while performing processing in background between events, using the difference between “electronic time” and “neural time” to achieve real-time performance. The model relaxes both local memory and update scheduling requirements to levels realistic for the hardware. The delayed-event model represents a useful way to recast the real-time updating problem into a question of time to the next event.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Indiveri, G., Chicca, E., Douglas, R.: A VLSI Array of Low-Power Spiking Neurons and Bistable Synapses With Spike-Timing Dependent Plasticity. IEEE Trans. Neural Networks 17(1), 211–221 (2006)
Mehrtash, N., Jung, D., Hellmich, H., Schönauer, T., Lu, V.T., Klar, H.: Synaptic Plasticity in Spiking Neural Networks (SP2INN): a System Approach. IEEE Trans. Neural Networks 14(5), 980–992 (2003)
Gerstner, W., Kempter, R., van Hemmen, J.L., Wagner, H.: A Neuronal Learning Rule for Sub-millisecond Temporal Coding. Nature 383(6595), 76–78 (1996)
Shadlen, M.N., Newsome, W.T.: The Variable Discharge of Cortical Neurons: Implications for Connectivity, Computation, and Information Coding. J. Neuroscience 18(10), 3870–3896 (1998)
Masuda, N., Aihara, K.: Duality of Rate Coding and Temporal Coding in Multilayered Feedfoward Networks. Neural Computation 15(1), 103–125 (2003)
Dayan, P., Abbott, L.: Theoretical Neuroscience. MIT Press, Cambridge (2001)
Goldberg, D., Cauwenberghs, G., Andreou, A.: Analog VLSI Spiking Neural Network With Address Domain Probabilistic Synapses. In: Proc. 2001 Int’l Symp. Circuits and Systems (ISCAS 2001), pp. 241–244 (2001)
Furber, S.B., Temple, S.: Neural Systems Engineering. J. Roy. Soc. Interface 4(13), 193–206 (2007)
Rast, A., Yang, S., Khan, M.M., Furber, S.: Virtual Synaptic Interconnect Using an Asynchronous Network-on-Chip. In: Proc. 2008 Int’l Joint Conf. Neural Networks (IJCNN 2008), pp. 2727–2734 (2008)
Plana, L.A., Furber, S.B., Temple, S., Khan, M.M., Shi, Y., Wu, J., Yang, S.: A GALS Infrastructure for a Massively Parallel Multiprocessor. IEEE Design & Test of Computers 24(5), 454–463 (2007)
Lazzaro, J., Wawrzynek, J., Mahowald, M., Silviotti, M., Gillespie, D.: Silicon Auditory Processors as Computer Peripherals. IEEE Trans. Neural Networks 4(3), 523–528 (1993)
Khan, M.M., Lester, D., Plana, L., Rast, A., Jin, X., Painkras, E., Furber, S.: SpiNNaker: Mapping Neural Networks Onto a Massively-Parallel Chip Multiprocessor. In: Proc. 2008 Int’l Joint Conf. Neural Networks (IJCNN 2008), pp. 2849–2856 (2008)
Izhikevich, E.: Simple Model of Spiking Neurons. IEEE Trans. Neural Networks 14, 1569–1572 (2003)
Jin, X., Furber, S., Woods, J.: Efficient Modelling of Spiking Neural Networks on a Scalable Chip Multiprocessor. In: Proc. 2008 Int’l Joint Conf. Neural Networks (IJCNN 2008), pp. 2812–2819 (2008)
Wang, H.P., Chicca, E., Indiveri, G., Sejnowski, T.J.: Reliable Computation in Noisy Backgrounds Using Real-Time Neuromorphic Hardware. In: Proc. 2007 IEEE Biomedical Circuits and Systems Conf. (BIOCAS 2007), pp. 71–74 (2007)
Daud, T., Duong, T., Tran, M., Langenbacher, H., Thakoor, A.: High Resolution Synaptic Weights and Hardware-in-the-Loop Learning. In: Proc. SPIE - Int’l Soc. Optical Engineering, vol. 2424, pp. 489–500 (1995)
Markram, H., Tsodyks, P.: Redistribution of Synaptic Efficacy Between Neocortical Pyramidal Neurons. Nature 382(6594), 807–810 (1996)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2009 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Rast, A., Jin, X., Khan, M., Furber, S. (2009). The Deferred Event Model for Hardware-Oriented Spiking Neural Networks. In: Köppen, M., Kasabov, N., Coghill, G. (eds) Advances in Neuro-Information Processing. ICONIP 2008. Lecture Notes in Computer Science, vol 5507. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-03040-6_128
Download citation
DOI: https://doi.org/10.1007/978-3-642-03040-6_128
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-03039-0
Online ISBN: 978-3-642-03040-6
eBook Packages: Computer ScienceComputer Science (R0)