Abstract
One major obstacle faced by designers when entering the multicore era is how to harness the massive computing power which these cores provide. Since Instructional-Level Parallelism (ILP) is inherently limited, one single thread is not capable of efficiently utilizing the resource of a single core. Hence, Simultaneous MultiThreading (SMT) microarchitecture can be introduced in an effort to achieve improved system resource utilization and a correspondingly higher instruction throughput through the exploitation of Thread-Level Parallelism (TLP) as well as ILP. However, when multiple threads execute concurrently in a single core, they automatically compete for system resources. Our research shows that, without control over the number of entries each thread can occupy in system resources like instruction fetch queue and/or reorder buffer, a scenario called “mutual-hindrance” execution takes place. Conversely, introducing active resource sharing control mechanisms causes the opposite situation (“mutual-benefit” execution), with a possible significant performance improvement and lower cache miss frequency. This demonstrates that active resource sharing control is essential for future multicore multithreading microprocessor design.
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References
Cazorla, F., Ramirez, A., Valero, M., Knijnenburg, P., Sakellariou, R., Fernandez, E.: QoS for high-performance SMT processors in embedded systems. IEEE Micro 24(4), 24–31 (2004)
Moore, G.E.: Cramming more components onto integrated circuits. Electronics 38(8), 114–117 (1965)
Asanovic, K., Bodik, R., Catanzaro, B.C., Gebis, J.J., Husbands, P., Keutzer, K., Patterson, D.A., Plishker, W.L., Shalf, J., Williams, S.W., Yelick, K.A.: The landscape of parallel computing research: a view from Berkeley. Technical Report UCB/EECS-2006-183, University of California at Berkeley (2006)
Hennessy, J.L., Patterson, D.A.: Computer Architecture: A Quantitative Approach, 4th edn. Morgan Kaufmann Publishers Inc., San Francisco (2006)
Vangal, S., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D., Singh, A., Jacob, T., Jain, S., Erraguntla, V., Roberts, C., Hoskote, Y., Borkar, N., Borkar, S.: An 80-tile sub-100-w teraflops processor in 65-nm CMOS. IEEE Journal of Solid-State Circuits 43(1), 29–41 (2008)
Zhang, Y.P., Jeong, T., Chen, F., Wu, H., Nitzsche, R., Gao, G.: A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture. In: IPDPS 20: Proceedings of the 20th International Parallel and Distributed Processing Symposium, p. 44. IEEE Computer Society, Los Alamitos (2006)
Tullsen, D., Eggers, S., Levy, H.: Simultaneous multithreading: Maximizing on-chip parallelism. In: ISCA 22: Proceedings of the 22nd Annual International Symposium on Computer Architecture, pp. 392–403. IEEE Computer Society Press, Los Alamitos (1995)
Tullsen, D., Eggers, S., Emer, J., Levy, H., Lo, J.L., Stamm, R.: Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor. In: ISCA 23: Proceedings of the 23rd Annual International Symposium on Computer Architecture, p. 191. IEEE Computer Society, Los Alamitos (1996)
Raasch, S., Reinhardt, S.: The impact of resource partitioning on SMT processors. In: PACT 2003: Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques, pp. 15–25. IEEE Computer Society, Los Alamitos (2003)
Cazorla, F.J., Ramirez, A., Valero, M., Fernandez, E.: Dynamically controlled resource allocation in SMT processors. In: MICRO 37: Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, pp. 171–182. IEEE Computer Society, Los Alamitos (2004)
Choi, S., Yeung, D.: Learning-based SMT processor resource distribution via hill-climbing. In: ISCA 2006: Proceedings of the 33rd Annual International Symposium on Computer Architecture, pp. 239–251. IEEE Computer Society, Los Alamitos (2006)
Wang, H., Koren, I., Krishna, C.M.: An adaptive resource partitioning algorithm for SMT processors. In: PACT 2008: Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, pp. 230–239. ACM Press, New York (2008)
Bower, F.A., Sorin, D.J., Cox, L.P.: The impact of dynamically heterogeneous multicore processors on thread scheduling. IEEE Micro 28(3), 17–25 (2008)
Knauerhase, R., Brett, P., Hohlt, B., Li, T., Hahn, S.: Using OS observations to improve performance in multicore systems. IEEE Micro 28(3), 54–66 (2008)
Nesbit, K.J., Moreto, M., Cazorla, F.J., Ramirez, A., Valero, M., Smith, J.E.: Multicore resource management. IEEE Micro 28(3), 6–16 (2008)
Kang, D., Liu, C., Gaudiot, J.L.: The impact of speculative execution on SMT processors. International Journal of Parallel Programming 36(4), 361–385 (2008)
Burger, D., Austin, T.M.: The simplescalar tool set, version 2.0. ACM SIGARCH Computer Architecture News 25(3), 13–25 (1997)
Henning, J.L.: SPEC CPU 2000: Measuring CPU performance in the new millennium. Computer 33(7), 28–35 (2000)
KleinOsowski, A.J., Lilja, D.J.: MinneSPEC: A new SPEC benchmark workload for simulation-based computer architecture research. IEEE Computer Architecture Letters 1(1), 7 (2002)
Luo, K., Gummaraju, J., Franklin, M.: Balancing thoughput and fairness in SMT processors. In: ISPASS 2001: Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software, pp. 164–171 (2001)
Liu, C., Gaudiot, J.L.: Resource sharing control in simultaneous multithreading microarchitectures. In: ACSAC 2008: Proceedings of the 13th Asia-Pacific Computer Systems Architecture Conference, pp. 1–8 (2008)
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Liu, C., Gaudiot, JL. (2009). The Impact of Resource Sharing Control on the Design of Multicore Processors. In: Hua, A., Chang, SL. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2009. Lecture Notes in Computer Science, vol 5574. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-03095-6_31
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DOI: https://doi.org/10.1007/978-3-642-03095-6_31
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