Abstract
This paper provides a survey on the existing proposals in the field of reconfigurable multithreading (ρMT) architectures. Until now, the reconfigurable architectures have been classified according to implementation or architectural criteria, but never based on their ρMT capabilities. More specifically, we identify reconfigurable architectures that provide implicit, explicit or no architectural support for ρMT. For each of the proposals, we discuss the conceptual model, the limitations and the typical application domains. We also summarize the main design problems and identify some key research questions related to highly efficient ρMT support. In addition, we discuss the application prospectives and propose possible research directions for future investigations.
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Vassiliadis, S., Wong, S., Cotofana, S.D.: The MOLEN μρ-coded processor. In: Brebner, G., Woods, R. (eds.) FPL 2001. LNCS, vol. 2147, pp. 275–285. Springer, Heidelberg (2001)
Heysters, P.M.: Coarse-grained reconfigurable computing for power aware applications. In: ERSA, pp. 272–280 (2006)
Seno, K., Yamazaki, M.: Virtual mobile engine (VME) LSI that “changes its spots” achievies ultralow power and diverse functionality. CX-News 42 (2005), http://www.sony.com
Ungerer, T., Robic, B., Silc, J.: A survey of processors with expliclicit multithreading. ACM Computing Surveys 35(1), 29–63 (2003)
Sima, M., Vassiliadis, S., Cotofana, S.D., van Eijndhoven, J.T.J., Vissers, K.A.: Field-programmable custom computing machines - a taxonomy. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 79–88. Springer, Heidelberg (2002)
Wigley, G.B., Kearney, D.A.: The first real operating system for reconfigurable computers. In: ACSAC, pp. 129–136. IEEE Computer Society Press, Los Alamitos (2000)
Wu, K., Kanstein, A., Madsen, J., Berekovic, M.: MT-ADRES: Multithreading on coarse-grained reconfigurable architecture. In: Diniz, P.C., Marques, E., Bertels, K., Fernandes, M.M., Cardoso, J.M.P. (eds.) ARCS 2007. LNCS, vol. 4419, pp. 26–38. Springer, Heidelberg (2007)
Mamidi, S., Schulte, M., Iancu, D., Glossner, J.: Architecture support for reconfigurable multithreaded processors in programmable communication systems. In: ASAP, pp. 320–327. IEEE Press, Los Alamitos (2007)
Uhrig, S., Maier, S., Kuzmanov, G.K., Ungerer, T.: Coupling of a reconfigurable architecture and a multithreaded processor core with integrated real-time scheduling. In: RAW, pp. 209–217 (2006)
Peck, W., Anderson, E., Agron, J., Stevens, J., Baijot, F., Andrews, D.: HTHREADS: a computational model for reconfigurable devices. In: FPL, pp. 885–888 (2006)
Compton, K., Hauck, S.: Reconfigurable computing: a survey of systems and software. ACM Computing Surveys 34(2), 171–210 (2002)
Diessel, O., Wigley, G.B.: Opportunities for operating systems research in reconfigurable computing. In: ACRC (1999)
So, H.K.-H., Brodersen, R.: A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH. ACM Transactions on Embedded Computing Systems 7(2), 1401–1407 (2008)
Zhou, B., Qui, W., Peng, C.-L.: An operating system framework for reconfigurable systems. In: CIT, pp. 781–787 (2005)
Noguera, J., Badia, R.M.: Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling. Trans. on Embedded Computing Sys. 3(2), 385–406 (2004)
Marescaux, T., Nollet, V., Mignolet, J.-Y., Bartic, A., Moffat, W., Avasare, P., Coene, P., Verkest, D., Vernalde, S., Lauwereins, R.: Run-time support for heterogeneous multitasking on reconfigurable SoCs. Integration 38(1), 107–130 (2004)
Zaykov, P.G., Kuzmanov, G.K., Gaydadjiev, G.N.: State-of-the-art reconfigurable multithreading architectures. Technical Report - CE-TR-2009-02 (2009)
The convey HC-1 computer, architecture overview (white paper), p. 11 (2008), http://www.conveycomputer.com
Gibeling, G., Schultz, A., Asanovic, K.: The RAMP architecture & description language. In: WARFP (2006)
Haynes, S.D., Epsom, H.G., Cooper, R.J., McAlpine, P.L.: UltraSONIC: A reconfigurable architecture for video image processing. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 482–491. Springer, Heidelberg (2002)
Satrawala, A., Varadarajan, K., Lie, M., Nandy, S., Narayan, R.: Redefine: Architecture of a soc fabric for runtime composition of computation structures. In: FPL 2007, pp. 558–561 (2007)
Wallner, S.: A reconfigurable multi-threaded architecture model. In: Omondi, A.R., Sedukhin, S.G. (eds.) ACSAC 2003. LNCS, vol. 2823, pp. 193–207. Springer, Heidelberg (2003)
Bauer, L., Shafique, M., Kreutz, S., Henkel, J.: Run-time system for an extensible embedded processor with dynamic instruction set. In: DATE, pp. 752–757 (2008)
Steiger, C., Walder, H., Platzner, M.: Heuristics for online scheduling real-time tasks to partially reconfigurable devices. In: FPL, pp. 575–584 (2003)
Zhou, X., Wang, Y., Huang, X.-Z., Peng, C.-L.: On-line scheduling of real-time tasks for reconfigurable computing system. In: FPT, pp. 57–64 (2006)
Angermeier, J., Teich, J.: Heuristics for Scheduling Reconfigurable Devices with Consideration of Reconfiguration Overheads. In: Proceedings 15th Reconfigurable Architectures Workshop, Miami, Florida (2008)
Resano, J., Mozos, D., Verkest, D., Catthoor, F.: A reconfiguration manager for dynamically reconfigurable hardware. IEEE Design & Test of Computers 22(5), 452–460 (2005)
Panainte, E.M.: The Molen compiler for reconfigurable architectures. Ph.D. dissertation, TU Delft (2007)
Li, Z., Hauck, S.: Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation. In: FPGA, pp. 187–195 (2002)
Steiger, C., Walder, H., Platzner, M., Thiele, L.: Online scheduling and placement of real-time tasks to partially reconfigurable devices. In: RTSS, pp. 224–235. IEEE Computer Society, Los Alamitos (2003)
Dittmann, F.: Methods to exploit reconfigurable fabrics - making reconfigurable systems mature. Ph.D. dissertation, University of Paderborn (2007)
Kalte, H., Porrmann, M.: Context saving and restoring for multitasking in reconfigurable systems. In: FPL, pp. 223–228. IEEE Press, Los Alamitos (2005)
Simmler, H., Levinson, L.: Multitasking on FPGA coprocessors. In: Grünbacher, H., Hartenstein, R.W. (eds.) FPL 2000. LNCS, vol. 1896, pp. 121–130. Springer, Heidelberg (2000)
Majer, M., Teich, J., Ahmadinia, A., Bobda, C.: The Erlangen Slot Machine: A dynamically reconfigurable fpga-based computer. VLSI Signal Processing 47(1), 15–31 (2007)
Ahmadinia, A., Bobda, C., Koch, D., Majer, M., Teich, J.: Task scheduling for heterogeneous reconfigurable computers. In: SBCCI, pp. 22–27 (2004)
Chen, Y., Chen, S.Y.: Cost-driven hybrid configuration prefetching for partial reconfigurable coprocessor. In: IPDPS, pp. 1–8. IEEE Press, Los Alamitos (2007)
Wallner, S.: Micro-task processing in heterogeneous reconfigurable systems. J. Comput. Sci. Technol. 20(5), 624–634 (2005)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2009 IFIP International Federation for Information Processing
About this paper
Cite this paper
Zaykov, P.G., Kuzmanov, G.K., Gaydadjiev, G.N. (2009). Reconfigurable Multithreading Architectures: A Survey. In: Bertels, K., Dimopoulos, N., Silvano, C., Wong, S. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2009. Lecture Notes in Computer Science, vol 5657. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-03138-0_29
Download citation
DOI: https://doi.org/10.1007/978-3-642-03138-0_29
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-03137-3
Online ISBN: 978-3-642-03138-0
eBook Packages: Computer ScienceComputer Science (R0)