Abstract
The provision of Quality of Service (QoS) in computing and communication environments has been the focus of much research in industry and academia during the last decades. A key component for networks with QoS support is the egress link scheduling algorithm. Apart from providing a good performance in terms of, for example, good end-to-end delay and fair bandwidth allocation, an ideal scheduling algorithm implemented in a high-performance network with QoS support should satisfy other important property which is to have a low computational and implementation complexity. This is especially important in high-performance networks due to their high speed and because switches are usually implemented in a single chip.
In [7] we proposed the Self-Clocked Fair Queuing Credit Aware (SCFQ-CA) and the Deficit Round Robin Credit Aware (DRR-CA) schedulers in order to adapt the SCFQ and DRR algorithms to networks with a link-level flow control mechanism. In this paper, we propose specific implementations of these two schedulers taking into account the characteristics of current high-performance networks. Moreover, we compare the complexity of these two algorithms in terms of silicon area and computation delay. In order to carry out this comparison, we have performed our own hardware implementation for the different schedulers. We have modeled the schedulers using the Handel-C language and employed the DK design suite tool from Celoxica in order to obtain hardware estimates on silicon area and arbitration time.
This work has been jointly supported by the Spanish MEC and European Comission FEDER funds under grants Consolider Ingenio-2010 CSD2006-00046 and TIN2006-15516-C04-02 and by Junta de Comunidades de Castilla-La Mancha under grant PCC08-0078-9856. Raúl Martínez was with the University of Castilla-La Mancha when the main ideas of the paper where developed.
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References
Blake, S., Back, D., Carlson, M., Davies, E., Wang, Z., Weiss, W.: An Architecture for Differentiated Services. Internet Request for Comment RFC 2475, Internet Engineering Task Force (December 1998)
Celoxica. Handel-C Language Reference Manual for DK4 (2005)
Cheng, L., Muralimanohar, N., Ramani, K., Balasubramonian, R., Carter, J.B.: Interconnect-aware coherence protocols for chip multiprocessors. In: ISCA, pp. 339–351. IEEE Computer Society, Los Alamitos (2006)
Demers, A., Keshav, S., Shenker, S.: Analysis and simulations of a fair queuing algorithm. In: SIGCOMM (1989)
Charny, A., et al.: Supplemental information for the new definition of EF PHB (Expedited Forwarding Per-Hop-Behavior). RFC 3247 (March 2002)
Golestani, S.J.: A self-clocked fair queueing scheme for broadband applications. In: INFOCOM (1994)
Martínez, R., Alfaro, F.J., Sánchez, J.L.: A framework to provide quality of service over Advanced Switching. IEEE Transactions on Parallel and Distributed Systems 19(8), 1111–1123 (2008)
Montessoro, P.L., Pierattoni, D.: Advanced research issues for tomorrow’s multimedia networks. In: International Symposium on Information Technology, ITCC (2001)
Parekh, A.K., Gallager, R.G.: A generalized processor sharing approach to flow control in integrated services networks: The single-node case. In: IEEE/ACM Transactions on Networking (1993)
Reinemo, S.A., Skeie, T., Sødring, T., Lysne, O., Trudbakken, O.: An overview of QoS capabilities in InfiniBand, Advanced Switching Interconnect, and Ethernet. IEEE Communications Magazine 44(7), 32–38 (2006)
Rexford, J., Greenberg, A.G., Bonomi, F.: Hardware-efficient fair queueing architectures for high-speed networks. In: INFOCOM (2), pp. 638–646 (1996)
Shreedhar, M., Varghese, G.: Efficient fair queueing using deficit round robin. In: SIGCOMM, pp. 231–242 (1995)
Sivaraman, V.: End-to-Ent delay service in high speed packet networks using Erliest Deadline First Scheduling. PhD thesis, University of California (2000)
Stiliadis, D., Varma, A.: Latency-rate servers: A general model for analysis of traffic scheduling algorithms. In: IEEE/ACM Transactions on Networking (1998)
Turner, J.S.: New directions in communications (or which way to the information age). IEEE Communications 24(10), 8–15 (1986)
Vellore, P., Venkatesan, R.: Performance analysis of scheduling disciplines in hardware. In: Canadian Conference on Electrical and Computer Engineering (CCECE) (May 2004)
Xilinx. Virtex-4 family overview. Fact sheet DS112 (v2.0) (June 2007)
Zhang, H.: Service disciplines for guaranteed performance service in packet-switching networks (1995)
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Martínez, R., Alfaro, F.J., Sánchez, J.L., Claver, J.M. (2009). Hardware Implementation Study of the SCFQ-CA and DRR-CA Scheduling Algorithms. In: Sips, H., Epema, D., Lin, HX. (eds) Euro-Par 2009 Parallel Processing. Euro-Par 2009. Lecture Notes in Computer Science, vol 5704. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-03869-3_100
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