Abstract
Sum of Absolute Difference (SAD) Computation is commonly used for motion estimation in video coding. It is usually the computationally intensive part in video processing. Therefore, a method to reduce the computational complexity is strictly required. In this paper, the effectiveness of saturation arithmetic on SAD computation is presented. Our goal is to use saturation arithmetic to reduce the complexity of SAD computation for the encoding process while the accuracy in finding the best matching block from the reference frame is still maintained. Experiment results show that the computational complexity of SAD computation is reduced efficiently by saving a number of bits for SAD values representation while the video quality is kept.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Wiegand, T., Sullivan, G., Bjontegaard, G., Luthra, A.: Overview of the H.264/AVC Video Coding Standard. IEEE Transactions on Circuits and System for Video Technology 13, 560–576 (2003)
Guevorkian, D., Launiainen, A., Liuha, P., Lappalainen, V.: Architectures for the Sum of Absolute Differences operation. In: IEEE Workshop on Signal Processing Systems – Conference Proceedings, pp. 57–62 (2002)
Constantinides, G., Cheung, P., Luk, W.: Synthesis of Saturation Arithmetic Architectures. ACM Transactions on Design Automation of Electronic Systems 8, 334–354 (2003)
Yadav, N., Schulte, M., Glossner, J.: Parallel Saturating Fractional Arithmetic Units. In: Proceedings of Ninth Great Lakes Symposium on VLSI, pp. 241–217 (1999)
Gall, D.: MPEG: A Video Compression Standard for Multimedia Applications. Communications of the ACM 34, 46–58 (1991)
Mitchell, J., Pennebaker, W., Fogg, C., LeGall, D.: MPEG Video Compression Standard. Springer Press, Heidelberg (1997)
Marpe, D., Schwarz, H., Wiegand, T.: Context-adaptive binary arithmetic coding in the H.264/AVC video compression standard. IEEE Transactions on Circuits and System for Video Technology 13, 620–636 (2003)
Lee, B., Fiskiran, M.: PLX: A Fully Subword-Parallel Instruction Set Architecture for Fast Scalable Multimedia Processing. In: IEEE International Conference on Multimedia and Expo – Conference Proceedings, pp. 117–120 (2002)
Peleq, A., Weiser, U.: MMX Technology Extension to the Intel Architecture. Micro, IEEE, 42 – 50 (1996)
Luo, Z., Lee, R.: Cost-Effective Multiplication with Enhanced Adders for Multimedia Applications. In: Proceedings of IEEE International Symposium on Circuits and Systems, vol. 1, pp. 651–654 (2000)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2009 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Tran, T.H., Cho, HM., Cho, SB. (2009). Performance Enhancement of Sum of Absolute Difference (SAD) Computation in H.264/AVC Using Saturation Arithmetic. In: Huang, DS., Jo, KH., Lee, HH., Kang, HJ., Bevilacqua, V. (eds) Emerging Intelligent Computing Technology and Applications. ICIC 2009. Lecture Notes in Computer Science, vol 5754. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-04070-2_45
Download citation
DOI: https://doi.org/10.1007/978-3-642-04070-2_45
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-04069-6
Online ISBN: 978-3-642-04070-2
eBook Packages: Computer ScienceComputer Science (R0)