Abstract
With the ever increasing growth of data communication in the field of e-commerce transactions and mobile communication data security has gained utmost importance. However the conflicting requirements of power, area and throughput of such applications make hardware cryptography an ideal choice. Dedicated hardware devices such as FPGAs can run encryption routines concurrently with the host computer which runs other applications. The use of error correcting code has proven to be are effective way to overcome data corruption in digital communication channel. In this paper, we describe the design and implementation of a reduced complexity decode approach along with minimum power dissipation FPGAs for Mobile Communication data security.
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© 2009 Springer-Verlag Berlin Heidelberg
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Menakadevi, T., Madheswaran, M. (2009). Design and Implementation of High Performance Viterbi Decoder for Mobile Communication Data Security. In: Herrero, Á., Gastaldo, P., Zunino, R., Corchado, E. (eds) Computational Intelligence in Security for Information Systems. Advances in Intelligent and Soft Computing, vol 63. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-04091-7_9
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DOI: https://doi.org/10.1007/978-3-642-04091-7_9
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-04090-0
Online ISBN: 978-3-642-04091-7
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