Abstract
Gigabit passive optical network (GPON) is likely to play an important role in future access networks and the current challenge is to increase the existing GPON bit-rate to 10 Gb/s to provide next generation access (NGA). However, implementing this in a cost-effective manner is difficult and an important research topic. One of the difficulties in implementation for the electronic part of high-speed GPON is the fragmentation feature as it requires multiple pipeline paths. This paper proposes a novel segmentation and reassembly (SAR) scheme, which simplifies the implementation of fragmentation in that it employs fewer FPGA resources and allows a faster hardware clock rate. Analysis confirms that the scheme does not suffer from reduced efficiency in a variety of conditions. It is also backward compatible and suitable for current 1.25 Gb/s and 2.5 Gb/s GPONs. The novel SAR is verified by both a hardware GPON emulator and a software OPNET simulation.
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© 2009 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering
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Qin, Y., Reed, M., Lu, Z., Hunter, D., Rafel, A., Kang, J. (2009). Fragmentation in a Novel Implementation of Slotted GPON Segmentation and Reassembly. In: Wang, C. (eds) AccessNets. AccessNets 2008. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 6. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-04648-3_18
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DOI: https://doi.org/10.1007/978-3-642-04648-3_18
Publisher Name: Springer, Berlin, Heidelberg
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