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Verifying VLSI Circuits

  • Conference paper
Automated Technology for Verification and Analysis (ATVA 2009)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 5799))

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Introduction

Circuit-level verification is a promising area for formal methods research. Simulation using tools such as SPICE remains the main method for circuit validation. Increasing integration densities have increased the prevalence of analog/mixed-signal designs. It is now common for analog components such as DLLs and phase correction circuits to be embedded deep in digital designs, making the circuits critical for chip functional yet hard to test. While digital design flows have benefited from systematic methodologies including the use of formal methods, circuit design remains an art. As a consequence, analog design errors account for a growing percentage of design re-spins. All of these have created a pressing need for better circuit-level CAD and motivated a strong interest in formal verification.

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Author information

Authors and Affiliations

  1. Department of Computer Science, University of British Columbia, Vancouver, BC, Canada

    Mark R. Greenstreet

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  1. Mark R. Greenstreet
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Editor information

Editors and Affiliations

  1. International Institute of Software Technology (UNI-IIST), United Nations University, Macao, China

    Zhiming Liu

  2. Department of Computer Science, Aalborg University, 9220, Aalborg, Denmark

    Anders P. Ravn

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Greenstreet, M.R. (2009). Verifying VLSI Circuits. In: Liu, Z., Ravn, A.P. (eds) Automated Technology for Verification and Analysis. ATVA 2009. Lecture Notes in Computer Science, vol 5799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-04761-9_1

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  • DOI: https://doi.org/10.1007/978-3-642-04761-9_1

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-04760-2

  • Online ISBN: 978-3-642-04761-9

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