Optimizing the Hardware Usage of Parallel FSMs

Abstract

Hardware design is traditionally done by modeling finite state machines (FSMs). In this paper, we present how a basic round-robing scheduling mechanism, well-known from operating systems, can be applied to a design that needs several identical FSMs running (quasi) in parallel.

This approach allows exploiting the classical trade-off between chip area and operating frequency to severely cut down the hardware resources needed to implement the FSMs by increasing the operating frequency of the design. We additionally show that, in a system-on-a-chip design using only a single clock domain, the design’s overall operating frequency is dependent on the processor’s frequency, making especially low-speed communication cores already clocked faster than needed. This means that with regard to the design’s frequency, our approach may come at no additional cost.