Abstract
This paper reports spreadsheet calculations intended to verify the timing of 6-4 GasP asynchronous Network on Chip (NoC) control circuits. The Logical Effort model used in the spreadsheet estimates the delays of each logic gate in the GasP control. The calculations show how these delays vary in response to differing environmental conditions. The important environmental variable is the physical distance from one GasP module to adjacent modules because longer wires present greater capacitance that retards the operation of their drivers. Remarkably, the calculations predict correct operation over a large range of distances provided the difference in the distances to predecessor and successor modules is limited, and predict failure if the distances differ by too much. Experimental support for this view comes from the measured behavior of a test chip called “Infinity” built by Sun Microsystems in 90 nanometer CMOS circuits fabricated at TSMC.
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Joshi, P., Beerel, P.A., Roncken, M., Sutherland, I. (2010). Timing Verification of GasP Asynchronous Circuits: Predicted Delay Variations Observed by Experiment. In: Dams, D., Hannemann, U., Steffen, M. (eds) Concurrency, Compositionality, and Correctness. Lecture Notes in Computer Science, vol 5930. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11512-7_17
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DOI: https://doi.org/10.1007/978-3-642-11512-7_17
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