Abstract
We address the problem of performance and power-efficient thread allocation in a CMP. To that end, based on analytical model, we introduce a parameterized performance/power metric that can be adjusted according to a preferred tradeoff between performance and power. We introduce an iterative threshold algorithm (ITA) for allocating threads to cores in the case of a single application with symmetric threads. We extend this to a simple and efficient heuristic for the case of multiple applications. We compare the performance/power metric value of ITA with constrained nonlinear optimization, pattern search algorithm and genetic algorithm. ITA outperforms the best of these methods by 9 while consuming on average 0.01% and at most 2.5% of the computational effort.
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References
Olukotun, K., Hammond, L.: The future of microprocessors. Queue 3, 26–29 (2005)
Spracklen, L., Abraham, S.G.: Chip Multithreading: Opportunities and Challenges. In: High-Performance Computer Architecture, pp. 248–252 (2005)
Barroso, L.A., Gharachorloo, K., McNamara, R., Nowatzyk, A., Qadeer, S., Sano, B., Smith, S., Stets, R., Verghese, B.: Piranha: a scalable architecture based on single-chip Multiprocessing. ACM SIGARCH Computer Architecture News, 282–293 (2000)
Guz, Z., Keidar, I., Kolodny, A., Weiser, U.: Nahalal: Memory Organization for Chip Multiprocessors. IEEE Computer Architecture Letters 6(1) (2007)
McCann, C., Vaswani, R., Zahojan, J.: A dynamic processor allocation policy for multi programmed shared memory multiprocessors. ACM Transactions on Computer Systems (1993)
Fedorova, A., Seltzer, M., Small, C., Nussbaum, D.: Performance of multithreaded chip multiprocessors and implications for operating system design. In: USENIX 2005 Annual Technical Conference, pp. 395–398 (2005)
Kim, S., Chandra, D., Solihin, Y.: Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture. In: 13th International Conference on Parallel Architecture and Compilation Techniques, pp. 111–122 (2004)
Yang, C., Chen, J., Kuo, T.: An Approximation Algorithm for Energy-Efficient Scheduling on A Chip Multiprocessor. IEEE Computer Society, 468–473 (2005)
Ding, Y., Kandemir, M., Irwin, M.J., Raghavan, P.: Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors. LNCS, vol. 5409, pp. 231–247. Springer, Heidelberg (2009)
Chen, G., Li, F., Son, S.W., Kandemir, M.: Application mapping for chip Multiprocessors. In: Proceedings of the 45th Annual Design Automation Conference, pp. 620–625 (2008)
Burd, T., Brodersen, R.W.: Energy efficient CMOS microprocessor design. In: 28th Hawaii International Conference on System Sciences, pp. 288–297 (1995)
Penzes, P.I., Martin, A.J.: Energy-delay efficiency of VLSI computations. In: Proceedings of the 12th ACM Great Lakes Symposium on VLSI, pp. 104–111 (2002)
Agarwal, A.: Performance tradeoffs in multithreaded processors. IEEE Transactions on Parallel and Distributed Systems 3(5), 525–539 (1992)
Benini, L., Bogliolo, A., De Micheli, G.: A survey of design techniques for system- level dynamic power management, pp. 231–248. Kluwer Academic Publishers, Dordrecht (2002)
Gonzalez, C.R., Woods, R.E.: Digital image processing, 3rd edn., pp. 128–138 (2008)
Bienia, C., Kumar, S., Singh, J.P., Li, K.: The PARSEC benchmark suite: characterization and architectural implications. In: Proceedings of the 17th international Conference on Parallel Architectures and Compilation Techniques, pp. 72–81 (2008)
Ben-Itzhak, Y., Cidon, I., Kolodny, A.: Performance and Power Aware CMP Thread Allocation Modeling. Technical Report, CCIT #735 (2009)
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Ben-Itzhak, Y., Cidon, I., Kolodny, A. (2010). Performance and Power Aware CMP Thread Allocation Modeling. In: Patt, Y.N., Foglia, P., Duesterwald, E., Faraboschi, P., Martorell, X. (eds) High Performance Embedded Architectures and Compilers. HiPEAC 2010. Lecture Notes in Computer Science, vol 5952. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11515-8_18
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DOI: https://doi.org/10.1007/978-3-642-11515-8_18
Publisher Name: Springer, Berlin, Heidelberg
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