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Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation

19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers

  • Conference proceedings
  • © 2010

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Editors:
  1. José Monteiro

    1. INESC-ID / IST, TU Lisbon, Lisbon, Portugal

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  2. René Leuken

    1. EEMCS/MECE/CAS, Delft University of Technology, Delft, The Netherlands

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    You can also search for this editor in PubMed   Google Scholar

Part of the book series: Lecture Notes in Computer Science (LNCS, volume 5953)

Part of the book sub series: Theoretical Computer Science and General Issues (LNTCS)

Included in the following conference series:

Conference proceedings info: PATMOS 2009.

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About this book

This book constitutes the thoroughly refereed post-conference proceedings of 19th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2009, featuring Integrated Circuit and System Design, held in Delft, The Netherlands during September 9-11, 2009. The 26 revised full papers and 10 revised poster papers presented were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on variability & statistical timing, circuit level techniques, power management, low power circuits & technology, system level techniques, power & timing optimization techniques, self-timed circuits, low power circuit analysis & optimization, and low power design studies.

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Table of contents (40 papers)

  1. Front Matter

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  3. Special Session

    1. SystemC AMS Extensions: New Language – New Methods – New Applications

      • Martin Barnasconi, Markus Damm, Karsten Einwich
      Pages 4-4

  4. Session 1: Variability & Statistical Timing

    1. Process Variation Aware Performance Analysis of Asynchronous Circuits Considering Spatial Correlation

      • Mohsen Raji, Behnam Ghavami, Hamid R. Zarandi, Hossein Pedram
      Pages 5-15

    2. Interpreting SSTA Results with Correlation

      • Zeqin Wu, Philippe Maurine, Nadine Azemard, Gille Ducharme
      Pages 16-25

    3. Residue Arithmetic for Variation-Tolerant Design of Multiply-Add Units

      • Ioannis Kouretas, Vassilis Paliouras
      Pages 26-35

    4. Exponent Monte Carlo for Quick Statistical Circuit Simulation

      • Paul Zuber, Vladimir Matvejev, Philippe Roussel, Petr Dobrovolný, Miguel Miranda
      Pages 36-45

  5. Poster Session 1: Circuit Level Techniques

    1. Clock Repeater Characterization for Jitter-Aware Clock Tree Synthesis

      • Monica Figueiredo, Rui L. Aguiar
      Pages 46-55

    2. A Hardware Implementation of the User-Centric Display Energy Management

      • Vasily G. Moshnyaga, Koji Hashimoto, Tadashi Suetsugu, Shuhei Higashi
      Pages 56-65

    3. On-chip Thermal Modeling Based on SPICE Simulation

      • Wei Liu, Andrea Calimera, Alberto Nannarelli, Enrico Macii, Massimo Poncino
      Pages 66-75

    4. Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures

      • Javier Castro, Pilar Parra, Antonio J. Acosta
      Pages 76-85

  6. Session 2: Power Management

    1. Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip

      • Iraklis Anagnostopoulos, Alexandros Bartzas, Dimitrios Soudris
      Pages 86-95

    2. Data-Driven Clock Gating for Digital Filters

      • Alberto Bonanno, Alberto Bocca, Alberto Macii, Enrico Macii, Massimo Poncino
      Pages 96-105

    3. Power Management and Its Impact on Power Supply Noise

      • Howard Chen, Indira Nair
      Pages 106-115

    4. Assertive Dynamic Power Management (AsDPM) Strategy for Globally Scheduled RT Multiprocessor Systems

      • Muhammad Khurram Bhatti, Muhammad Farooq, Cécile Belleudy, Michel Auguin, Ons Mbarek
      Pages 116-126

  7. Session 3: Low Power Circuits & Technology

    1. Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique

      • Chih-Hsiang Lin, James B. Kuo
      Pages 127-135

    2. Crosstalk in High-Performance Asynchronous Designs

      • Ritej Bachhawat, Pankaj Golani, Peter A. Beerel
      Pages 136-145

    3. Modeling and Reducing EMI in GALS and Synchronous Systems

      • Tomasz Król, Milos Krstić, Xin Fan, Eckhard Grass
      Pages 146-155
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Other volumes

  1. Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation

Editors and Affiliations

  • INESC-ID / IST, TU Lisbon, Lisbon, Portugal

    José Monteiro

  • EEMCS/MECE/CAS, Delft University of Technology, Delft, The Netherlands

    René Leuken

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