Abstract
Leakage power dissipation has become a critical issue in advanced pro cess technologies. The use of techniques to reduce leakage power consumption with negligible degradation in performances is needed for current and next tech nologies. Power gating is an effective technique to reduce leakage, taking advantage of the transistor stacking effect. However, the restoration from standby mode in power-gated circuits usually introduces a large amount of switching noise on the power supply and ground networks, that may affect the normal operation of circuits connected to the same polarizations. This paper analyzes the switching noise generated in the wake-up phase by several power-gat ing techniques, and their influence on the wake-up time. The best results are for the techniques that redistribute the amount of current flowing through the Vdd and Gnd nodes during the wake-up transition. Simulation results obtained on basic digital cells in a 90 nm technology show a variation of two in switching noise, while maintaining the same wake-up time and leakage saving.
This is a preview of subscription content, log in via an institution to check access.
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Roy, K., Prasad, S.C.: Low-Power CMOS VLSI Circuit Design. Wiley-Interscience, Hoboken (2000)
Henzler, S.: Power Management Of Digital Circuits In Deep Sub-Micron CMOS Technologies. Springer Series in Advanced Microelectronics (2007)
Narendra, S.G., Chandrakasan, A.: Leakage in Nanometer CMOS Technologies. Springer, Heidelberg (2006)
Aragonès, X., González, J.L., Rubio, A.: Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs. Kluwer Academic Publishers, Dordrecht (1999)
Kim, S., et al.: Reducing ground-bounce noise and stabilizing the data-retention voltage of power-gating structures. IEEE Trans. on Electron Devices 55(1), 197–205 (2008)
Kim, S., Kosonocky, S.V., Knebel, D.R.: Understanding and minimizing ground bounce during mode transition of power gating structures. In: Proc. of ISLPED, pp. 22–25 (2003)
Usami, K., et al.: Design and implementation of fine-grain power gating with ground bounce suppression. In: 22nd Conf. on VLSI Design, pp. 381–386 (2009)
Kim, S., et al.: Minimizing inductive noise in system-on-a-chip with multiple power gating structures. In: Proc. of the 29th ESSCIRC, pp. 635–638 (2003)
Pakbaznia, E., Fallah, F., Pedram, M.: Charge recycling in MTCMOS circuits: concept and analysis. In: Proc. of the 43rd DAC, pp. 97–102 (2006)
Pakbaznia, E., Fallah, F., Pedram, M.: Charge recycling in power-gated CMOS circuits. IEEE Trans. on CAD 27(10), 1798–1811 (2008)
Deepaksubramanyan, B.S., Núñez, A.: Analysis of subthreshold leakage reduction in CMOS digital circuits. In: Proc. of 50th MWSCAS, pp. 1400–1404 (2007)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2010 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Castro, J., Parra, P., Acosta, A.J. (2010). Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures. In: Monteiro, J., van Leuken, R. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2009. Lecture Notes in Computer Science, vol 5953. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11802-9_12
Download citation
DOI: https://doi.org/10.1007/978-3-642-11802-9_12
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-11801-2
Online ISBN: 978-3-642-11802-9
eBook Packages: Computer ScienceComputer Science (R0)