Abstract
This paper presents a low-power soft error-hardened latch suitable for reliable circuit operation. The proposed circuit uses redundant feedback loop to protect latch against soft error on the internal nodes, and transmission gate and Schmitt-trigger circuit to filter out transient resulting from particle hit on combinational logic. The proposed circuit has low power consumption with negative setup time and low timing overhead. The HSPICE post-layout simulation in 90nm CMOS technology reveals that circuit is able to recover from almost any single particle strike on internal nodes and tolerates input SETs up to 130ps of duration.
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References
Baumann, R.: Soft Errors in Advanced Computer Systems. IEEE Design and Test of Computers 22(3), 258–266 (2005)
Mitra, S., Zhang, M., Mak, T.M., Seifert, N., Zia, V., Kim, K.S.: Logic soft errors: a major barrier to robust platform design. In: Proc. Int. Test Conference, November 2005, pp. 687–696 (2005)
Omana, M., Rossi, D., Metra, C.: Latch susceptibility to transient faults and new hardening approach. IEEE Trans. Comput. 56(9), 1255–1268 (2007)
Seifert, N., Shipleg, P., Pant, M.D., Ambrose, V., Gil, B.: Radiation induced clock jitter and race. In: Int. Physics Reliability Symposium, April 2005, pp. 215–22 (2005)
Shivakumar, P., Kistler, M., Keckler, S.W., Burger, D., Alvisi, L.: Modeling the effect of technology trends on the soft error rate of combinational logic. In: Proc. Int’l Conference on Dependable Systems and Networks (DSN), June 2002, pp. 389–399 (2002)
Kastensmidt, F., Sterpone, L., Sonza Reorda, M., Carrro, L.: On the optimal design of triple modular redundancy logic for SRAM-based FPGAs. In: Proc. IEEE Design, Automation and Test in Europe, pp. 1290–1295 (2005)
Fazeli, M., Miremadi, S.G., Ejlali, A., Patooghy, A.: Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies. IET Computers & Digital Techniques 3(3), 289–303 (2009)
Karnik, T., Vangal, S., Veeramachaneni, V., Hazucha, P., Erraguntla, V., Borkar, S.: Selective node engineering for chip-level soft error rate improvement. In: IEEE Symp. VLSI Circuits, June 2002, pp. 204–205 (2002)
Calin, T., Nicolaidis, M., Velazco, R.: Upset hardened memory design for submicron CMOS technology. IEEE Trans. Nucl. Sci. 43, 2874–2878 (1996)
Hazucha, P., Karnik, T., Walstra, S., Bloechel, B.A., Tschanz, J.W., Maiz, J., Soumyanath, K., Dermer, G.E., Narendra, S., De, V., Borkar, S.: Measurements and analysis of SER-tolerant latch in a 90-nm dual-VT CMOS process. IEEE Journal of Solid-State Circuits 39(9), 1536–1543 (2004)
Sasaki, Y., Namba, K., Ito, H.: Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger. J. Electron. Test., 11–19 (June 2008)
Oklobdzija, V.G.: Clocking and Clocked Storage Elements in a Multi-Gigahertz Environment. IBM J. of Research and Development 47(5/6), 567–584 (2003)
Kumar, J., Tahoori, M.B.: Use of pass transistor logic to minimize the impact of soft errors in combinational circuits. In: Workshop on System Effects of Logic Soft Errors (2005)
Das, S., Tokunaga, C., Pant, S., Ma, W.-H., Kalaiselvan, S., Lai, K., Bull, D.M., Blaauw, D.T.: RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance. IEEE J. of Solid-State Circuits 44(1), 32–48 (2009)
Dabiri, F., Nahapetian, A., Massey, T., Potkonjak, M., Sarrafzadeh, M.: General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems 27(10), 1788–1797 (2008)
Mitra, S., Seifert, N., Zhang, M., Shi, Q., Kim, K.S.: Robust system design with built-in soft-error resilience. Computer 38(2), 43–52 (2005)
Narasimham, B., Bhuva, B.L., Holman, W.T., Schrimpf, R.D., Massengill, L.W., Witulski, A.F., Robinson, W.H.: The Effect of Negative Feedback on Single Event Transient Propagation in Digital Circuits. IEEE Trans. on Nuclear Science 53(6), 3285–3290 (2006)
Narasimham, B., Shuler, R.L., Black, J.D., Bhuva, B.L., Schrimpf, R.D., Witulski, A.F., Holman, W.T., Massengill, L.W.: Quantifying the Reduction in Collected Charge and Soft Errors in the Presence of Guard Rings. IEEE Trans. on Device and Materials Reliability 8(1), 203–209 (2008)
Stackhouse, B., Bhimji, S., Bostak, C., Bradley, D., Cherkauer, B., Desai, J., Francom, E., Gowan, M., Gronowski, P., Krueger, D., Morganti, C., Troyer, S.: A 65 nm 2-Billion Transistor Quad-Core Itanium Processor. IEEE J. of Solid-State Circuits 44(1), 18–31 (2009)
Degalahal, V., Ramanarayanan, R., Vijaykrishnan, N., Xie, Y., Irwin, M.J.: Effect of Power Optimizations on Soft Error Rate. In: IFIP Series on VLSI-SoC, pp. 1–20. Springer, Heidelberg (2006)
Oklobdzija, V.G., Stojanovic, V.M., Markovic, D.M., Nedovic, N.: Digital System Clocking: High Performance and Low-Power Aspects. Wiley-IEEE (2005)
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Karimiyan Alidash, H., Oklobdzija, V.G. (2010). Low-Power Soft Error Hardened Latch. In: Monteiro, J., van Leuken, R. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2009. Lecture Notes in Computer Science, vol 5953. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11802-9_30
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DOI: https://doi.org/10.1007/978-3-642-11802-9_30
Publisher Name: Springer, Berlin, Heidelberg
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